- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379886 > CH7202 (Electronic Theatre Controls, Inc.) MPEG to TV Encoder with 8-bit Input PDF資料下載
參數(shù)資料
| 型號： | CH7202 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MPEG to TV Encoder with 8-bit Input |
| 中文描述： | 電視的MPEG編碼器8位輸入 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 110K |
| 代理商： | CH7202 |
CHRONTEL
CH7202
6
201-0000-030 Rev 2.0, 6/2/99
General Description
The CH7202 is a fully integrated solution for converting 8-bit YCrCb (4:2:2) digital video inputs into high-
quality NTSC or PAL video signals while generating all essential clock signals for MPEG playback. All
essential circuitry for this conversion and clock generation (Dual PLL’s, linear interpolator, digital filters,
NTSC/PAL encoder, DAC’s) are contained in the CH7202 making it an essential component of any low-cost
solution for video-CD playback machines. Refer to the Block Diagram on page 1 and the Interface Diagram on
page 5.
Functional Description
The encoded luminance (Y) and color-difference (U,V) values are interpolated and filtered through digital
filters to minimize aliasing problems. The filtered signals go to the digital encoder where they are transformed
to composite and S-video outputs, and then they are converted by the three 9-bit DACs to analog outputs.
8-bit YCrCb (4:2:2) Input
Y data and CrCb data are multiplexed into the CH7202 through the YC[7:0] pins. The order of the multiplexed
data is determined by the YCSWAP and CbSWAP pins, and is referenced to the horizontal sync pin. Refer to
Figure5
on page 7.
Clock/Data/Synchronization Timing
The CH7202 can operate in either master or slave mode. In master mode, it supplies the necessary clocks (1X,
2X, video system and audio) and synchronization (HSYNC* and VSYNC*) signals to other building blocks in
the video system. In slave mode, the 2X pixel clock, HSYNC* and VSYNC* become inputs to the CH7202,
and the remaining clock signals are still output. The timing relationships are shown in
Figures 6
and
7
on
page 8.
Video Encoder Modes
Combinations of the two signals MOD0 and MOD1 select the various TV signal format and power saving
modes as shown below.
Table 3 Video Encoder Modes
Frequency Select Modes
The frequency select input FS affects the DCLK and ACLK outputs as shown below.
FS = 1 (default) DCLK = 40.5 MHz, ACLK = 16.934 MHz
FS = 0
DCLK = 33.9 MHz, ACLK = 11.289 MHz
MOD1
MOD0
Video Encoder Mode
1
1
NTSC
1
0
PAL
0
1
PAL-M
0
0
Sleep mode (Encoder off, both PLLs running)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CH7203 | MPEG to TV Encoder with 16-bit Input |
| CH7203-V | MPEG to TV Encoder with 16-bit Input |
| CH7301A | Chrontel CH7301 DVI Output Device |
| CH7301A-T | Chrontel CH7301 DVI Output Device |
| CH7301A-T-A | Chrontel CH7301 DVI Output Device |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CH7203 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MPEG to TV Encoder with 16-bit Input |
| CH7203-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MPEG to TV Encoder with 16-bit Input |
| CH720S-40PT | 制造商:CHENMKO 制造商全稱:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.04 Ampere |
| CH721C276MA80A8 | 制造商:AVX Corporation 功能描述: |
| CH721UPT | 制造商:CHENMKO 制造商全稱:Chenmko Enterprise Co. Ltd. 功能描述:SCHOTTKY BARRIER DIODE VOLTAGE 40 Volts CURRENT 0.2 Ampere |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。