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參數(shù)資料
| 型號(hào)： | CGS74CT2525N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | EIGHT DISTRIBUTED-OUTPUT CLOCK DRIVER|ACT-CMOS|DIP|14PIN|PLASTIC |
| 中文描述： | ACT SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDIP14 |
| 封裝： | 0.300 INCH WIDE, DIP-14 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 170K |
| 代理商： | CGS74CT2525N |
AC Electrical Characteristics
Over recommended operating conditions unless specified otherwise. (Continued)
(Note 6)
Range
(V)
V
CC
CGS74CT
54ACT
CGS74CT
T
A
e a
25
§
C
C
L
e
50 pF
T
A
e b
55
§
C
to
a
125
§
C
C
L
e
50 pF
T
A
e b
40
§
C
to
a
85
§
C
C
L
e
50 pF
Symbol
Parameter
Units
Min
Typ
Max
Min
Max
Min
Typ
Max
t
PLH
,
t
PHL
Propagation Delay
SEL to O
n
(’2526)
5.0
5.1
8.5
12.4
4.4
14.1
ns
t
OSHL
Maximum Skew
Common Edge
Output-to-Output (Note 7)
Variation
5.0
0.2
550
ps
t
OSLH
Maximum Skew
Common Edge
Output-to-Output (Note 7)
Variation
5.0
0.2
550
ps
t
OST
Maximum Skew
Opposite Edge
Output-to-Output (Note 7)
Variation
5.0
0.4
1.0
ns
t
PV
Maximum Skew
Part-to-Part
Variation (Note 8)
AC2525
ACT2525
AC2526
5.0
3.5
ns
ACT2526
5.0
5.0
ns
t
rise
,
t
fall
Maximum
Rise/Fall Time
(20% to 80% V
CC
)
5.0
3.0
3.75
ns
t
rise
,
t
fall
Maximum
Rise/Fall Time
(0.8V/2.0V and 2.0V/0.8V)
0.9
1.1
ns
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
I
IN
and I
CC
@
3.0V are guaranteed to be less than or equal to the respective limit
@
5.5V V
CC
.
I
CC
for 54AC
@
25
§
C is identical to CGS74C
@
25
§
C.
Note 4:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 5:
I
CC
for 54ACT
@
25
§
C is identical to CGS74CT
@
25
§
C.
Note 6:
Voltage Range 5.0 is 5.0V
g
0.5V, voltage range 3.3 is 3.3V
g
0.3V.
Note 7:
Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
) or in opposite directions both
HL and LH (t
OST
). t
OSHL
and t
OSLH
are characterized and guaranteed by design
@
1 MHz.
Note 8:
Part-to-part skew is defined as the absolute value of the difference between the propagation delay for any outputs from device to device. The parameter is
specified for a given set of conditions (i.e., capacitive load, V
CC
, temperature,
Y
of outputs switching, etc.). Parameter guaranteed by design.
Note 9:
Load capacitance includes the test jig.
http://www.national.com
6
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相關(guān)代理商/技術(shù)參數(shù) |
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| CGS74CT2525N/NOPB | 制造商:National Semiconductor Corporation 功能描述:Clock Fanout Buffer 8-OUT 14-Pin PDIP 制造商:National Semiconductor 功能描述:Clock Fanout Buffer 8-OUT 14-Pin PDIP |
| CGS74CT2525W | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| CGS74CT2526 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:1-to-8 Minimum Skew Clock Driver |
| CGS74CT2526E | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Eight Distributed-Output Clock Driver |
| CGS74CT2526J | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Eight Distributed-Output Clock Driver |
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