參數(shù)資料
型號： CGS3314MX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： Miscellaneous Clock Generator
中文描述： 13.75 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝： 0.150 INCH, MS-012, SOIC-8
文件頁數(shù)： 5/7頁
文件大?。?/td> 116K
代理商： CGS3314MX
5
www.fairchildsemi.com
C
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the DC and AC
Electrical Characteristics tables are not guaranteed at the absolute maxi-
mum ratings. The Recommended Operating Conditions will define the con-
ditions for actual device operation.
DC Electrical Characteristics
Supply Voltage (V
CC
)
DC Input Voltage Diode Current (I
IK
)
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
SOIC
0.5V to 7.0V
±
9 mA
0.5V to 7.0V
±
20 mA
-0.5V to V
CC
+
0.5V
±
70 mA
55
°
C to 150
°
C
140
°
C/W
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
4.5V to 5.5V
0V to 5.5V
0V to V
CC
V
40
°
to
+
85
°
C
Symbol
V
IHTTL
Parameter
Minimum HIGH Level
Input Voltage,
TTL Level Inputs (OEH, OEL)
Maximum LOW Level
Input Voltage, TTL Level
Inputs (OEH, OEL)
Minimum HIGH Level
Input Voltage. CMOS
Level Inputs (DIVA)
Maximum LOW Level
Input voltage. CMOS
Level Inputs (DIVA)
Minimum Logic 1 Input
for Three Level Input
(DIVB, OSC_DR)
T
A
=
+
25
°
C
T
A
=
40
°
C to
+
85
°
C
Units Conditions
V
V
CC
(V)
4.5
Typ
Guaranteed Limits
Min
2.0
Max
Min
2.0
Max
5.5
2.0
2.0
V
ILTTL
4.5
0.8
0.8
V
5.5
0.8
0.8
V
IHCMOS
4.5
3.15
3.15
V
5.5
3.85
3.85
V
ILCMOS
4.5
1.35
1.35
V
5.5
1.65
1.65
V
IN3L_H
4.5
4.05
4.05
V
5.5
4.95
4.95
V
IN3L_1/2
Minimum Logic 1/2 Input
for Three Level Input
(DIVB, OSC_DR)
4.5
5.5
1.8
2.2
2.7
3.3
1.8
2.2
2.7
3.3
V
V
IN3L_L
Maximum Logic 0 Input
Level Three Level Input
(DIVB, OSC_DR)
4.5
5.5
0.45
0.45
0.45
0.45
V
V
OH
Minimum HIGH Level
Output Voltage
4.5
5.5
4.5
4.49
5.49
4.40
5.40
3.86
4.40
5.40
3.76
V
I
OUT
=
50
μ
A
I
OH
=
48 mA
V
IN
=
V
IH
or V
IH
I
OUT
=
50
μ
A
5.5
4.5
5.5
4.86
4.76
V
OL
Minimum LOW Level
Output Voltage
0.001
0.001
0.1
0.1
0.1
0.1
V
4.5
5.5
5.5
0.44
0.44
360
0.44
0.44
380
I
OL
=
+
48mA
V
IN
=
V
IL
or V
IH
V
IN
=
5.5V
I
IHRES
Input Current for Pins
DIVB, OSC_DR, and
DIVA (Input is Logic HIGH)
Input Current for Pins
DIVB, OSC_DR, and
DIVA (Input is Logic LOW)
Input Current for
Enable Pin OEL
Input Current for
Enable Pin OEH
220
200
μ
A
I
ILRES
5.5
220
360
200
380
μ
A
VIN
=
0.0V
I
IHENAB
5.5
90
160
85
175
μ
A
V
IN
=
5.5V
I
ILENAB
5.5
90
160
85
175
μ
A
V
IN
=
0.0V
I
IHOSC
Input Current for OSC_IN Pin
(Indicates Bias Resistance)
Input Current for OSC_IN Pin
(Indicates Bias Resistance)
Output Disabled Current
(Output HIGH)
5.5
20
100
20
125
μ
A
V
IN
=
5.5V
I
ILOSC
5.5
20
100
20
125
μ
A
V
IN
=
0.0V
I
OZH
4.5
5.5
3.0
3.0
5.0
5.0
μ
A
V
OUT
=
V
CC
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