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參數(shù)資料
| 型號(hào)： | CGS3312 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | CMOS Crystal Clock Generators(CMOS晶體時(shí)鐘發(fā)生器) |
| 中文描述： | 水晶時(shí)鐘發(fā)生器的CMOS的CMOS（晶體時(shí)鐘發(fā)生器） |
| 文件頁(yè)數(shù)： | 3/7頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | CGS3312 |
3
www.fairchildsemi.com
C
Truth Tables
Division Selection
Note:
Actual value of the floating OSC_DR and DIVB input is V
CC/2
Rise and Fall Time Selection
Drive Selection
Note:
Where “F” indicates floating the input.
Pin Descriptions
Functional Table
Summary of Device Options
Each drive has one output with the choices of selecting frequency divide,
output enable, crystal drive and output rise and fall time. Crystal drive
options are:
L
=
LOW Drive
M
=
MEDIUM Drive
H
=
HIGH Drive
DIVB DIVA OEL
F
0/F
1
0/F
0
0/F
F
1
1
1
0
1
X
X
OEH
X
1
1
1
1
1
X
Divider Output
Divide-by 1
Divide-by 2
Divide-by 4
Divide-by 8
Divide-by 16
Divide-by 32
Output Reset HIGH
at Re-enable
Output Reset HIGH
at Re-enable
X
0
0
0
0
0
1
X
X
X
0
OSC_DR DIV TRF Rise/Fall Time (ns)
F
N
0/F
F
N
1
F
Y
0/F
F
Y
1
0,1
X
0/F
0,1
X
1
2
less than 2
4
2
4
2
OSC_DR
0
1
F
Drive
Low
Medium
High
Note: Pin out varies for each device.
OSC_IN
Input to Oscillator Inverter. The output of the
crystal would be connected here.
OEL
Active LOW 3-STATE enable pin. This pin pulls
to a low value when left floating and 3-STATE
the output when forced HIGH. This pin has TTL
compatible input levels.
Rise and Fall time override pin. Available only
for die form.
This pin is the main clock output on the device.
OSC_OUT Resistive Buffered Output of the Oscillator
Inverter
OSC_DR
3 Level input pin that selects Oscillator Drive
Level
DIVA
Input used to select Binary Divide-by Option.
This pin has CMOS compatible input levels.
OEH
Active HIGH 3-STATE enable pin. This pin pulls
to a high value when left floating and 3-STATEs
the output when forced low. This pin has TTL
compatible input levels.
TRF
OUT
OSCLO_1
The Oscillator LOW pin is the ground for the
Oscillator.
This pin is the same signal as OSCLO_1. It has
been provided as an alternate connection for
OSCLO_1 for hybrid assemblies.
OSCLO_2
V
CC
GND
The power pin for the chip.
The ground pin for all sections of the circuitry
except the oscillator and oscillator related
circuitry.
Device
3311
3312
3313
3314
3315
3316
3317
3318
3319
Divide
1, 2, 4
1, 2, 4
8, 16, 32
8, 16, 32
1, 2, 4
4
32
1, 2, 4
1, 2, 4
Enable
OEH
OEH
OEH
OEH
OEL
OEH
OEH
OEH
OEL
Drive
L, M, H
H
H
L, M, H
H
H
H
H
L, M, H
Output Rise/
Fall Time (ns)
2, 4
2, 4
4
4
1, 2
4
4
1, 2
2, 4
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| CGS3312M | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CMOS Cry Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CGS3312MX | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CMOS Cry Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CGS3312N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Miscellaneous Clock Generator |
| CGS3313M | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CMOS Cry Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CGS3313MX | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CMOS Cry Clock Gen RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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