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參數(shù)資料
| 型號： | CGS2536V |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Commercial, Industrial Quad 1 to 4 Clock Drivers |
| 中文描述： | 2536 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 127K |
| 代理商： | CGS2536V |
Power On Requirements
DETAILED DESCRIPTION
The divide by two block of the CGS2536 is accomplished
using two negative-edge-triggered flip-flops. During power-
on, the inverting flip-flop causes outputs Aout1 through
Dout1 to be High. The non-inverting flip-flop causes outputs
Aout0 through Dout0 to be Low. Two flip-flops are used to
achieve minimum skew between the non-inverting and in-
verting outputs.
To guarantee that the flip-flops power-up out of phase, the
IN0 and IN1 pins must be held low while power is applied to
V
CC
. IN0 and IN1 must remain low until V
CC
t
3V.
Application Hints
In a typical user environment IN0 and IN1 inputs may be
connected common. Power is applied simultaneously to the
crystal oscillator and the CGS2536. If the oscillator output
does not deliver a clean first negative-going-edge to the IN0
and IN1 inputs, only one flip-flop may toggle.
Even if the user delays application of V
CC
to the CGS2536,
a false trigger may occur. Simply gating the oscillator to the
IN0 and IN1 inputs will not guarantee correct operation,
since a ‘‘runt’’ pulse may propagate through the gate and
toggle only one of the flip-flops.
Figure 1 shows a circuit that delivers ‘‘runt-free’’ negative-
going-edges to the IN0 and IN1 inputs. This circuit ensures
that the first clocking pulse seen by the IN0 and IN1 inputs
consists of a full positive half-cycle of the crystal oscillator.
Figure 2 shows the waveforms from the synchronizing cir-
cuit.
The propagation delay of the 74AC00 gates and the toggle
frequency of the 74VHC164 limit the maximum frequency of
operation. Equivalent logic elements that have faster propa-
gation delays can be substituted for the NAND gates and
shift register. For example, a generic GAL22V10-5 could be
programmed as the NAND gates that drive the CGS2536.
Figure 1 CIRCUIT DESCRIPTION
Assumptions:
1. V
CC
is applied simultaneously to the crystal oscillator,
CGS2536, 74AC00, and 74VHC164.
2. A system power-on reset is ‘‘Low’’ long enough for V
CC
and the crystal oscillator to stabilize.
At power-on, assertion (low) of the system power-on reset
clears the outputs of the 74VHC164 serial to parallel con-
verter.
As a result, nodes C and E are low ensuring power-on re-
quirements for the CGS2536 are met. When the system
power-on reset is de-asserted, the eighth positive-going-
edge received by the 74VHC164 causes node C to go high.
Node C remains high as long as power is applied. However,
node D still remains high due to the oscillator output (A)
being low. Node E stays low until the next positive-going-
edge of the oscillator. Thus, a full positive half-cycle of the
oscillator is seen by the IN1 and IN0 inputs, which ensures
that both flip-flops of the divide by two toggle.
TL/F/12325–4
TL/F/12325–5
5
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