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參數(shù)資料
| 型號(hào)： | CGS2535V |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Commercial Quad 1 to 4 Clock Drivers/Industrial Quad 1 to 4 Clock Drivers(商用四路4選1時(shí)鐘驅(qū)動(dòng)器/工業(yè)用途四路4選1的時(shí)鐘驅(qū)動(dòng)器) |
| 中文描述： | 2535 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大小： | 69K |
| 代理商： | CGS2535V |
CGS2534/35/36/37
Memory Array Driving
In order to minimize the total load on the address bus, quite
often memory arrays are driven by buffers while having the
inputs of the buffers tied together. Although this practice was
feasible in the conventional memory designs, in today’s high
speed, large buswidth designs which require address fetch-
ing at higher speeds, this technique produces many undes-
ired results such as cross-talk and over/undershoot.
CGS2534/35/36/37 Quad 1 to 4 clock drivers were designed
specifically to address these application issues on high
speed, large memory arrays systems.
These drivers are optimized to drive large loads, with 3.5 ns
propagation delays. These drivers produce less noise while
reducing the total capacitive loading on the address bus by
having only four inputs tied together (see the diagram below,
point A). This helps to minimize the overshoot and under-
shoot by having only four outputs being switched simulta-
neously.
Also this larger fan-out helps to save board space since for
every one of these drivers, two conventional buffers were
typically being used.
Another feature associated with these clock drivers is a
350 ps pin-to-pin skew specification. The minimum skew
specification allows high speed memory system designers to
optimize the performance of their memory sub-system by
operating at higher frequencies without having concerns
about output-to-output (bank-to-bank) synchronization prob-
lems which are associated with driving high capacitive loads
(Point B).
The diagram below depicts a “2534/35/36/37” a memory
subsystem operating at high speed with large memory ca-
pacity. The address bus is common to both the memory and
the CPU and I/Os.
These drivers can operate beyond 125 MHz, and are also
available in 3V–5V TTL/CMOS versions with large current
drive .
Device
2534
2535
2536
2537
V
CC
5
3 or 5
3 or 5
5
I/O
TTL
CMOS
CMOS
TTL
Output Configuration
Inverting quad 1–4
Non-inverting quad 1–4
Inverting, Non-inverting,
÷
2
Inverting quad 1–4 with series 8
output resistors
DS011954-8
5
http:\\www.national.com
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CGS2536TV | Commercial, Industrial Quad 1 to 4 Clock Drivers |
| CGS2536V | Commercial, Industrial Quad 1 to 4 Clock Drivers |
| CGS3319MX | Miscellaneous Clock Generator |
| CGS3312 | CMOS Crystal Clock Generators(CMOS晶體時(shí)鐘發(fā)生器) |
| CGS3311 | CMOS Crystal Clock Generators(CMOS晶體時(shí)鐘發(fā)生器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CGS2535V/NOPB | 制造商:National Semiconductor Corporation 功能描述:Clock Fanout Buffer 16-OUT 28-Pin PLCC 制造商:National Semiconductor 功能描述:Clock Fanout Buffer 16-OUT 28-Pin PLCC |
| CGS2535VNOPB | 制造商:National Semiconductor Corporation 功能描述:Clock Fanout Buffer 16-OUT 28-Pin PLCC 制造商:National Semiconductor 功能描述:Clock Fanout Buffer 16-OUT 28-Pin PLCC |
| CGS2535VX | 功能描述:IC CLK BUFFER 4:16 125MHZ 28PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無(wú) 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| CGS2535VX/NOPB | 制造商:National Semiconductor Corporation 功能描述:Clock Fanout Buffer 16-OUT 28-Pin PLCC T/R 制造商:National Semiconductor 功能描述:Clock Fanout Buffer 16-OUT 28-Pin PLCC T/R |
| CGS2535VXNOPB | 制造商:National Semiconductor Corporation 功能描述:Clock Fanout Buffer 16-OUT 28-Pin PLCC T/R 制造商:National Semiconductor 功能描述:Clock Fanout Buffer 16-OUT 28-Pin PLCC T/R |
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