- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379830 > CDC338 (Texas Instruments, Inc.) Phase-lock Loop Clock Driver with 3 state Output(鎖相環(huán)時鐘驅(qū)動器(三態(tài)輸出)) PDF資料下載
參數(shù)資料
| 型號： | CDC338 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Phase-lock Loop Clock Driver with 3 state Output(鎖相環(huán)時鐘驅(qū)動器(三態(tài)輸出)) |
| 中文描述： | 鎖相3態(tài)輸出環(huán)路時鐘驅(qū)動器（鎖相環(huán)時鐘驅(qū)動器（三態(tài)輸出）） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 153K |
| 代理商： | CDC338 |
CDC338
PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS418 – MAY 1992 – REVISED FEBRUARY 1993
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
PIN
I/O
DESCRIPTION
NAME
NO.
CLKIN
16
I
This input pin provides the clock signal to be distributed by the CDC338 clock driver circuit. This clock signal is used
to provide the reference signals to the integrated phase-lock loops that generate the clock-output signals. This signal
must have a fixed frequency and fixed phase in order for these phase-lock loops to obtain phase lock. Once the circuit
is powered up and a valid CLKIN signal is applied, a stabilization time is required for the phase-lock loops to phase
lock their feedback signals to their reference signals.
This input pin is used to reset the HF output signal to a known phase. It is useful to ensure that HF output signals
of multiple CDC338 circuits are all in the same phase. The CLR signal is a negative-edge-triggered signal. When
a high-to-low edge occurs at CLR, the flip-flop that divides the CLKIN signal to provide reference for the HF
phase-lock loop is asynchronously cleared to a low level. Following the required stabilization time, HF output signals
for all CDC338 units that receive the same CLKIN and CLR signals will have the same phase. In order for the clear
function to operate in a deterministic fashion, the circuit must be allowed to stabilize from power up before using this
function.
CLR
12
I
DF
18
O
This output pin is used to transmit a double-frequency clock signal. This signal is phase locked to the CLKIN signal
via a phase-lock loop that operates at twice the frequency of the reference CLKIN signal. Due to normal operation
of the phase-lock loop, the duty cycle of the DF signal will be nominally 50% independent of the duty cycle of the
CLKIN signal.
HF
14
O
This output pin is used to transmit a half-frequency clock signal. This signal is phase locked to the CLKIN signal via
a phase-lock loop that operates at half the frequency of the reference CLKIN signal. Due to normal operation of the
phase-lock loop, the duty cycle of the HF signal will be nominally 50% independent of the duty cycle of the CLKIN
signal. Since the phase of the HF signal cannot be determined at power up, the CLR input has been provided to allow
the HF signals of multiple CDC338 circuits to be reset to the same phase.
This input pin is the output enable for all outputs. When OE is low, all outputs are enabled. When OE is high, all outputs
are in the high-impedance state. Since the feedback signal for each phase-lock loop is taken directly from the
appropriate output pin, placing the outputs in the high-impedance state interrupts the feedback loop. Therefore, when
a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is required before the
phase-lock loops obtain phase lock.
These output pins are used to transmit same-frequency clock signals. These signals are each phase locked to the
CLKIN signal via individual phase-lock loops that operate at the same frequency as the reference CLKIN signal. Due
to normal operation of the phase-lock loop, the duty cycle of the Y output signals will be nominally 50% independent
of the duty cycle of the CLKIN signal.
OE
20
I
Y1–Y4
2, 4,
7, 9
O
timing diagram
HF
CLKIN
CLR
Y
DF
OE
NOTE: This diagram is applicable only after any appropriate stabilization time has elapsed.
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDC339DWR | Eight Distributed-Output Clock Driver |
| CDC421XXX | FULLY INTEGRATED FIXED FREQUENCY LOW-JITTER, CRYSTAL-OSCILLATOR CLOCK GENERATOR |
| CDC4D20 | POWER INDUCTORS <SMD Type> |
| CDC5D23B | POWER INDUCTORS <SMD Type> |
| CDC509PW | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDC338DW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Six Distributed-Output Clock Driver |
| CDC339 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CLOCK DRIVER WITH 3-STATE OUTPUTS |
| CDC339DB | 功能描述:時鐘驅(qū)動器及分配 1-To-8 Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC339DBG4 | 功能描述:時鐘驅(qū)動器及分配 1-To-8 Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDC339DBLE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CLOCK DRIVER WITH 3-STATE OUTPUTS |
發(fā)布緊急采購，3分鐘左右您將得到回復。