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| 型號(hào)： | CDC2510BPW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
| 中文描述： | 3.3 - V相位鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大小： | 146K |
| 代理商： | CDC2510BPW |
CDC2510B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS612 – SEPTEMBER 1998
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
AVCC, VCC
MIN
TYP
MAX
UNIT
VIK
II = –18 mA
IOH = –100
μ
A
IOH = –12 mA
IOH = –6 mA
IOL = 100
μ
A
IOL = 12 mA
IOL = 6 mA
VI = VCC or GND
VI = VCC or GND,
One input at VCC – 0.6 V,
VI = VCC or GND
VO = VCC or GND
3 V
–1.2
V
MIN to MAX
VCC–0.2
VOH
3 V
2.1
V
3 V
2.4
MIN to MAX
0.2
VOL
3 V
0.8
V
3 V
0.55
±
5
10
II
ICC§
ICC
Ci
Co
3.6 V
μ
A
μ
A
μ
A
pF
IO = 0, Outputs: low or high
Other inputs at VCC or GND
3.6 V
3.3 V to 3.6 V
500
3.3 V
4
3.3 V
6
pF
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§For ICC of AVCC and ICC vs Frequency (see Figures 7 and 8).
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
fclk
Clock frequency
25
125
MHz
Input clock duty cycle
Stabilization time
40%
60%
1
ms
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 30 pF (see Note 6 and Figures 1 and 2)
PARAMETER
FROM
(INPUT)/CONDITION
TO
(OUTPUT)
VCC, AVCC = 3.3 V
±
0.165 V
VCC, AVCC = 3.3 V
±
0.3 V
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
tphase error, – jitter
(see Notes 7 and 8,
Figures 3, 4, and 5)
tsk(o)§
Jitter(pk-pk)(see Figure 6)
Jitter(cycle-cycle)
(See Figure 6)
CLKIN
↑
= 66 MHz to 100 MHz
FBIN
↑
–150
150
–200
200
ps
Any Y or FBOUT
Any Y or FBOUT
200
ps
Any Y or FBOUT
–80
80
Clkin = 66 MHz to 100 MHz
Any Y or FBOUT
|100|
ps
Duty cycle reference
(see Figure 4)
F(clkin > 60 MHz)
Any Y or FBOUT
45%
55%
tr
tf
Any Y or FBOUT
1.3
1.9
0.8
2.1
ns
Any Y or FBOUT
1.7
2.5
1.2
2.7
ns
These parameters are not production tested.
§The tsk(o) specification is only valid for equal loading of all outputs.
NOTES:
6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
7. This is considered as static phase error.
8. Phase error does not include jitter. The total phase error is –230 ps to 230 ps for the 5% VCC range.
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