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參數(shù)資料
| 型號： | CDB4351 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 10/37頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS4351 DAC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Popguard® |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電壓 |
| 工作溫度： | -10°C ~ 70°C |
| 已供物品： | 板，纜線，CD |
| 已用 IC / 零件： | CS4351 |
| 產(chǎn)品目錄頁面： | 757 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS4351-DZZ-ND - IC DAC STER 112DB 192KHZ 20TSSOP 598-1055-5-ND - IC DAC STER 112DB 192KHZ 20TSSOP |
| 其它名稱： | 598-1152 |
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18
DS566F1
CS4351
4.4.1
Stand-Alone Mode
When pulled to VL the DEM pin activates the 44.1 kHz de-emphasis filter. When pulled to GND the DEM
pin turns off the de-emphasis filter.
4.4.2
Control Port Mode
The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see Section 6.2.2
for the desired de-emphasis control.
4.5
Recommended Power-Up Sequence
4.5.1
Stand-Alone Mode
1.
Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in Section 4.2. In this state, the control
port is reset to its default settings, VQ will remain low, and VBIAS will be connected to VA.
2.
Bring RST high. The device will remain in a low power state with VQ low and will initiate the Stand-
Alone power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK
cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.5.2
Control Port Mode
1.
Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in Section 4.2. In this state, the control port is reset to its
default settings, VQ will remain low, and VBIAS will be connected to VA.
2.
Bring RST high. The device will remain in a low power state with VQ low.
3.
Perform a control port write to the CP_EN bit prior to the completion of approximately 512 LRCK
cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in
Quad-Speed Mode). The desired register settings can be loaded while keeping the PDN bit set to 1.
4.
Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 s when
the POPG bit is set to 0. If the POPG bit is set to 1, see Section 4.6 for a complete description of
power-up timing.
4.6
Popguard Transient Control
The CS4351 uses a novel technique to minimize the effects of output transients during power-up and power-
down. This technology, when used with external DC-blocking capacitors in series with the audio outputs,
minimizes the audio transients commonly produced by single-ended single-supply converters. It is activated
inside the DAC when the RST pin is toggled and requires no other external control, aside from choosing the
appropriate DC-blocking capacitors.
4.6.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTA and AOUTB, are clamped to GND.
Following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies-
cent voltage. Approximately 10,000 LRCK cycles later, the outputs reach VQ and audio output begins.
This gradual voltage ramping allows time for the external DC-blocking capacitors to charge to the quies-
cent voltage, minimizing audible power-up transients.
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