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參數(shù)資料
| 型號： | CDB42L51 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 36/43頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS42L51 CODEC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻編解碼器 |
| 嵌入式： | 是，其它 |
| 已用 IC / 零件： | CS42L51，CS8406，CS8415 |
| 主要屬性： | 立體聲數(shù)字音頻發(fā)射器和接收器 |
| 次要屬性： | 圖形用戶界面，S/PDIF 接口 |
| 已供物品： | 板，CD |
| 相關(guān)產(chǎn)品： | CS42L51-DNZR-ND - IC CODEC STEREO W/HDPN AMP 32QFN 598-1627-ND - IC CODEC STEREO W/HDPN AMP 32QFN CS42L51-CNZR-ND - IC CODEC LOW-V 24BIT 32-QFP 598-1045-ND - IC CODEC STEREO W/HDPN AMP 32QFN |
| 其它名稱： | 598-1005 |
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DS679F1
41
CS42L51
4.7
Initialization
The initialization and Power-Down sequence flowchart is shown in Figure 22 on page 42. The CODEC en-
ters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma modu-
lators and control port registers are reset. The internal voltage reference, multi-bit DAC and ADC and
switched-capacitor low-pass filters are powered down.
The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-
cessible once RESET is high and the desired register settings can be loaded per the interface descriptions
in “Software Mode” on page 43. If a valid write sequence to the control port is not made within approximately
10 ms, the CODEC will enter Hardware Mode.
Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage references, DAC_FILT+ and
ADC_FILT+ will begin powering up to normal operation. The charge pump slowly powers up and charges
the capacitors. Power is then applied to the headphone amplifiers and switched-capacitor filters, and the an-
alog/digital outputs enter a muted state. Once LRCK is valid, MCLK occurrences are counted over one LRCK
period to determine the MCLK/LRCK frequency ratio and normal operation begins.
4.8
Recommended Power-Up Sequence
1.
Hold RESET low until the power supplies are stable.
2.
Bring RESET high. After approximately 10 ms, the device will enter Hardware Mode.
3.
For Software Mode operation, set the PDN bit to ‘1’b in under 10 ms. This will place the device in “stand-
by”.
4.
Load the desired register settings while keeping the PDN bit set to ‘1’b.
5.
Start MCLK to the appropriate frequency, as discussed in Section 4.5.
6.
Set the PDN bit to ‘0’b.
7.
Apply LRCK,SCLK and SDIN for normal operation to begin.
8.
Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
LRCK
SCLK
MS B
LS B
MS B
LS B
L e ft C han ne l
R ig h t C h an n e l
SDIN
MSB
AOUTA / AINxA
AOUTB / AINxB
Figure 20. Left-Justified Format
LRCK
SCLK
MS B
LS B
MS B
LS B
Left C han ne l
R ig h t C han ne l
SDIN
AOUTA
AOUTB
Figure 21. Right-Justified Format (DAC only)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB42L51/FAE | 制造商:Cirrus Logic 功能描述:EVAL BOARD FOR THE CS42L51 PORTABLE STEREO CODEC - Bulk |
| CDB42L52 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd LP CODEC w/classD Spkr Driver RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB42L52/FAE | 制造商:Cirrus Logic 功能描述:EVAL BD LOW-VOLTAGE STEREO CODEC - Bulk |
| CDB42L55 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd Ultra Low PWR Stereo Codec RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| CDB42L56 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 24Bit Ultra LP Ster CD w/clH HP RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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