參數(shù)資料
型號(hào)： CDB4271
廠商： Cirrus Logic Inc
文件頁數(shù)： 17/29頁
文件大?。?/td> 0K
描述： EVAL BOARD CS4271 STEREO CODEC
標(biāo)準(zhǔn)包裝： 1
主要目的： 音頻編解碼器
嵌入式： 是，F(xiàn)PGA / CPLD
已用 IC / 零件： CS4271
主要屬性： 立體聲 24 位 192 kHz 采樣率
次要屬性： I²S，S/PDIF 輸入和輸出，模擬輸入和輸出，GUI
已供物品： 板，纜線，CD
產(chǎn)品目錄頁面： 754 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： CS4271-DZZR-ND - IC CODEC 24BIT 114DB 28-TSSOP
CS4271-DZZ-ND - IC CODEC 24BIT 114DB 28-TSSOP
598-1041-5-ND - IC CODEC AUD 24BIT 114DB 28TSSOP
其它名稱： 598-1003
CS4271
24
DS592F1
5. APPLICATIONS
5.1
Stand-Alone Mode
5.1.1
Recommended Power-Up Sequence
1) When using the CS4271 with an external MCLK, hold RST low until the power supply, MCLK, and LRCK are
stable. When using the CS4271 with internally generated MCLK, hold RST low until the power supply is stable.
2) Bring RST high. If the internally generated MCLK is being used, it will appear on the MCLK pin prior to 1 ms from
the release of RST.
5.1.2
Master/Slave Mode
The CS4271 supports operation in either Master Mode or Slave Mode.
In Master Mode, LRCK and SCLK are outputs and are synchronously generated on-chip. LRCK is equal to Fs and
SCLK is equal to 64x Fs.
In Slave Mode, LRCK and SCLK are inputs, requiring external generation that is synchronous to MCLK. It is recom-
mended that SCLK be 64x Fs to maximize system performance.
In Stand-Alone Mode, the CS4271 will default to Slave Mode. Master Mode may be accessed by placing a 47 k
pull-up to VL on the SDOUT (M/S) pin.
Configuration of clock ratios in each of these modes will be outlined in the Tables 3 and 4.
5.1.3
System Clocking
The CS4271 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed
modes as shown in Table 1 below.
5.1.3.1
Crystal Applications (XTI/XTO)
An external crystal may be used in conjunction with the CS4271 to generate the master clock signal. To accomplish
this, a 20 pF fundamental mode parallel resonant crystal must be connected between the XTI and XTO pins as
shown in the Typical Connection Diagram on page 23. This crystal must oscillate at the frequency shown in Table 2.
In this configuration, MCLK is a buffered output and, as shown in the Typical Connection Diagram, nothing other
than the crystal and its load capacitors should be connected to XTI and XTO. The MCLK signal will appear on the
MCLK pin prior to 1 ms from the release of RST.
To operate the CS4271 with an externally generated MCLK signal, no crystal should be used, XTI should be con-
nected to ground and XTO should be left unconnected. In this configuration, MCLK is an input and must be driven
externally with an appropriate speed clock.
Table 1. Speed Modes
Mode
Sampling Frequency
Single Speed
4-50 kHz
Double Speed
50-100 kHz
Quad Speed
100-200 kHz
Table 2. Crystal Frequencies
Mode
Crystal Frequency
Single Speed
512 x Fs
Double Speed
256 x Fs
Quad Speed
128 x Fs
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