參數(shù)資料
型號: CAT34WC02UITE13C
元件分類: EEPROM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 該CAT24FC02是一個2 KB的EEPROM的國內(nèi)256個8位每字舉辦的串行CMOS
文件頁數(shù): 5/10頁
文件大?。?/td> 284K
代理商: CAT34WC02UITE13C
DsconinuedPat
START
CAT34WC02
5
Doc No. 1003, Rev. O
2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT34WC02 monitor the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed
(except when accessing the Write Protect Register) as
1010 for the CAT34WC02 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
and define which device the Master is accessing. Up to
eight CAT34WC02 may be individually addressed by
the system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT34WC02 monitors the bus and
its address matches the transmitted slave address. The
CAT34WC02 then performs a Read or a Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT34WC02 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT34WC02 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT34WC02 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
34WC02 F07
Figure 4. Acknowledge Timing
Figure 5. Slave Address Bits
ACKNOWLEDGE
1
SCL FROM
MASTER
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
1
DEVICE ADDRESS
0
1
0
A2
A1
A0
R/W
0
1
1
0
A2
A1
A0
R/W
Normal Read and Write
Programming the Write
Protect Register
相關(guān)PDF資料
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CAT34WC02UITE13E The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT34WC02YITE13A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
CAT34WC02YITE13C The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CAT34WC02UITE13E 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2-kb I2C Serial EEPROM, Serial Presence Detect
CAT34WC02U-TE13 制造商:ON Semiconductor 功能描述:EEPROM Serial-I2C 2K-Bit 256 x 8 3.3V/5V 8-Pin TSSOP T/R
CAT34WC02W 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM
CAT34WC02W-1.8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM
CAT34WC02W-1.8TE13 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EEPROM