參數(shù)資料
型號(hào): CAT24C208
英文描述: 8-Kb Dual Port Serial EEPROM
中文描述: 8 KB的雙端口串行EEPROM
文件頁數(shù): 7/13頁
文件大小: 194K
代理商: CAT24C208
CAT24C208
7
Doc No. 1044, Rev. F
2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
DEVICE ADDRESSING
DDC Interface
Both the DDC and DSP interfaces to the device are
based on the I
2
C bus serial interface. All memory space
operations are done at the A0/A1 DDC address pair. As
such, all write operations to the memory space are done
at DDC address A0h and all read operations of the
memory space are done at DDC address A1h.
Figure 3 shows the bit sequence of a random read from
anywhere within the memory space. The word offset
determines which of the 256 bytes within segment 00h
Figure 3. Random Access Read (Segment 00h only)
Figure 4. Sequential Read (Segment 00h only)
WORD OFFSET
T
R
A
T
S
0
0
0
0
0
1
0
1
K
C
A
S
S
E
R
D
D
A
0
A
-
7
A
K
C
A
T
R
A
T
S
1
0
0
0
0
1
0
1
K
C
A
A
T
A
D
K
C
A
O
N
P
O
T
S
T
R
A
T
S
0
0
0
0
0
1
0
1
K
C
A
0
S
A
E
-
R
7
D
A
D
S
A
K
C
A
T
R
A
T
S
1
0
0
0
0
1
0
1
K
C
A
0
A
T
A
D
K
C
A
.
N
A
T
A
D
K
C
A
O
N
P
O
T
S
Figures 5 and 6 show the byte and page write respectively. The configuration register must have the WE bit set to 1
prior to any write on DDC Port. Only the segment 00h can be accessed of either lower or upper bank.
Figure 5. Byte Write (Segment 00h only)
T
R
A
T
S
0
0
0
0
0
1
0
1
K
C
A
S
S
E
R
D
D
A
0
A
-
7
A
K
C
A
A
T
A
D
K
C
A
P
O
T
S
Figure 6. Page Write (Segment 00h only)
T
R
A
T
S
0
0
0
0
0
1
0
1
K
C
A
S
S
E
R
D
D
A
0
A
-
7
A
K
C
A
0
A
T
A
D
K
C
A
.
5
1
A
T
A
D
K
C
A
P
O
T
S
WORD OFFSET
WORD OFFSET
WORD OFFSET
is being read. Here the segment 00h can be at the lower
or upper bank depending on the configuration register.
Sequential reads can be done in much the same manner
by reading successive bytes after each acknowledge
without generating a stop condition. See Figure 4. The
device automatically increments the word offset value
(8-bit value) and with wraparound in the same segment
00h to read maximum of 256 bytes.
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