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參數(shù)資料
| 型號： | CAT24C03VP2I-T |
| 元件分類： | EEPROM |
| 英文描述： | 2-Kb I2C CMOS Serial EEPROM with Partial Array Write Protection |
| 中文描述： | 2 KB的的CMOS串行EEPROM的I2C偏陣列寫保護 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 410K |
| 代理商： | CAT24C03VP2I-T |
CAT24C03
3
Doc No. 1113, Rev. A
2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A.C. CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= -40
°
C to 85
°
C, unless otherwise specified.
Symbol
F
SCL
T
I(1)
Parameter
Clock Frequency
1.8 V - 5.5 V
Min
2.5 V - 5.5 V
Min
Units
kHz
Max
100
Max
400
Noise Suppression Time Constant at
SCL, SDA Inputs
SCL Low to SDA Data Out
0.1
0.1
μ
s
t
AA(2)
t
BUF(1)
3.5
0.9
μ
s
Time the Bus Must be Free Before a
New Transmission Can Start
Start Condition Hold Time
4.7
1.3
μ
s
t
HD:STA
4
0.6
μ
s
t
LOW
Clock Low Period
4.7
1.3
μ
s
t
HIGH
Clock High Period
4
0.6
μ
s
t
SU:STA
Start Condition Setup Time
4.7
0.6
μ
s
t
HD:DAT
Data In Hold Time
0
0
μ
s
t
SU:DAT
t
R(1)
t
F(1)
Data In Setup Time
0.25
0.1
μ
s
SDA and SCL Rise Time
1
0.3
μ
s
SDA and SCL Fall Time
0.3
0.3
μ
s
t
SU:STO
Stop Condition Setup Time
4
0.6
μ
s
t
DH
Data Out Hold Time
0.1
0.1
μ
s
t
WR
Write Cycle Time
5
5
ms
t
PU(1), (3)
Power-up to Ready Mode
1
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) For timing measurements the SDA line capacitance is ~ 100 pF; the SCL input is driven with rise and fall times of < 50 ns; the SDA I/O
is pulled-up by a 3 mA current source; input driving signals swing from 20% to 80% of V
CC
. Output level reference levels are 30% and
respectively 70% of V
CC
.
(3) t
PU
is the delay required from the time V
CC
is stable until the device is ready to accept commands.
Power-On Reset (POR)
The CAT24C03 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
The CAT24C03 will power up into Standby mode after
V
CC
exceeds the POR trigger level and will power
down into Reset mode when V
CC
drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
The POR circuitry triggers at the minimum V
CC
level
required for proper initialization of the internal state
machines. The POR trigger level automatically tracks the
internal CMOS device thresholds, and is naturally well
below the minimum recommended V
CC
supply voltage.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CAT24C03VP2IT3 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM |
| CAT24C03VP2I-T3 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection |
| CAT24C03WI-3 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection |
| CAT24C03WI-G | 功能描述:電可擦除可編程只讀存儲器 (256x8) 2K 1.8 - 5.5 Industrial Temp RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT24C03WI-G3 | 制造商:CATALYST 制造商全稱:Catalyst Semiconductor 功能描述:2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection |
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