參數(shù)資料
型號(hào): CAT24C03LI-T
元件分類: EEPROM
英文描述: 2-Kb I2C CMOS Serial EEPROM with Partial Array Write Protection
中文描述: 2 KB的的CMOS串行EEPROM的I2C偏陣列寫保護(hù)
文件頁數(shù): 6/20頁
文件大?。?/td> 410K
代理商: CAT24C03LI-T
CAT24C03
6
Doc. No. 1113, Rev. A
2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WRITE OPERATIONS
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, byte address and data to be written
(Figure 5). The Slave acknowledges all 3 bytes, and the
Master then follows up with a STOP, which in turn starts
the internal Write operation (Figure 6). During internal
Write, the Slave will not acknowledge any Read or Write
request from the Master.
Page Write
The CAT24C03 contains 256 bytes of data, arranged
in 16 pages of 16 bytes each. A page is selected by the
4 most significant bits of the address byte following the
Slave address, while the 4 least significant bits point to
the byte within the page. Up to 16 bytes can be written
in one Write cycle (Figure 7).
The internal byte address counter is automatically in-
cremented after each data byte is loaded. If the Master
transmits more than 16 data bytes, then earlier bytes will
be overwritten by later bytes in a ‘wrap-around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT24C03 is busy writing or is ready to accept com-
mands. Polling is implemented by interrogating the
device with a ‘Selective Read’ command (see READ
OPERATIONS).
The CAT24C03 will not acknowledge the Slave address,
as long as internal Write is in progress.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is pro-
tected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation
of the CAT24C03.
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