FN957.10 July 11, 2005 Metallization Mask Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as" />
參數(shù)資料
型號(hào): CA3140MZ
廠商: Intersil
文件頁(yè)數(shù): 14/23頁(yè)
文件大小: 0K
描述: IC OPAMP BIMOS 4.5MHZ 8SOIC
標(biāo)準(zhǔn)包裝: 98
放大器類型: 通用
電路數(shù): 1
轉(zhuǎn)換速率: 9 V/µs
增益帶寬積: 4.5MHz
電流 - 輸入偏壓: 10pA
電壓 - 輸入偏移: 5000µV
電流 - 電源: 4mA
電流 - 輸出 / 通道: 40mA
電壓 - 電源,單路/雙路(±): 4 V ~ 36 V,±2 V ~ 18 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
產(chǎn)品目錄頁(yè)面: 1233 (CN2011-ZH PDF)
21
FN957.10
July 11, 2005
Metallization Mask Layout
Dimensions in parenthesis are in millimeters and are derived
from the basic inch dimensions as indicated. Grid graduations
are in mils (10-3 inch).
The photographs and dimensions represent a chip when it is
part of the wafer. When the wafer is cut into chips, the cleavage
angles are 57o instead of 90ο with respect to the face of the
chip. Therefore, the isolated chip is actually 7 mils (0.17mm)
larger in both dimensions.
62-70
(1.575-1.778)
4-10
(0.102-0.254)
60
50
40
30
20
10
0
58-66
(1.473-1.676)
50
40
30
20
10
61
0
60
65
CA3140, CA3140A
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