參數(shù)資料
型號(hào)： CA16
英文描述： CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
中文描述： CA16型2.5 Gb /秒的DWDM轉(zhuǎn)發(fā)器，16通道155 Mbits /秒復(fù)用器/解復(fù)用器
文件頁(yè)數(shù)： 23/30頁(yè)
文件大?。?/td> 464K
代理商： CA16
23
Agere Systems Inc.
Advance Data Sheet
March 2001
CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Timing Characteristics
(continued)
PHERR/PHINIT
Case 1—PHERR and PHINIT are shorted on the
printed-circuit board:
PHINIT would go high whenever there is a potential tim-
ing mismatch between PC
LK
and PIC
LK
. PHINIT would
remain high as long as the timing mismatch between
PC
LK
and PIC
LK
. If PHINIT is high for more than two
byte clocks, the FIFO will be initialized. PHINIT will ini-
tialize the FIFO two-to-eight byte clocks after it is high
for at least two byte clocks, PHERR (and thus PHINIT)
goes active once the FIFI is initialized.
Case 2—PHERR signal is input to the customer logic
and the customer logic outputs a signal to PHINIT:
Another possible configuration is where the PHERR
signal is input into the customer logic and the customer
logic sends an output to the PHINIT input. However,
the customer logic must ensure that, upon detecting a
high on PHERR, the PHINIT signal remains high for
more than two byte clocks. If PHINIT is high for less
than two byte clocks, the FIFO is not guaranteed to be
initialized. Also, the customer logic must ensure that
PHINIT goes low after the FIFO is initialized (PHERR
goes low).
Figure 9. PHERR/PHINIT Timing
PHERR
PHINIT
PCLK
PICLK
INTERNAL
PCLK
MINIMUM PULSE
WIDTH REQUIRED
TO CENTER
THE FIFO
2 BYTE
CLOCKS
2—8 BYTE CLOCKS
CUSTOMER ASIC SENDS A
MINIMUM PULSE WIDTH OF
2 BYTE CLOCKS UPON DETECTING
A HIGH ON PHERR
FIFO IS INITIALIZED 2—8 BYTE CLOCKS
AFTER PHINIT IS HIGH FOR 2 BYTE CLOCKS
PHERR GOES HIGH ON
DETECTING A FIFO TIMING ERROR
1125(F)
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CA16A2Cnn CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer
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