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參數(shù)資料
| 型號(hào)： | CA10 |
| 廠商： | Littelfuse, Inc. |
| 英文描述： | SURFACE MOUNT ESD SUPPRESSORS, 8-Line CA10 |
| 中文描述： | 表面貼裝ESD抑制器，8線CA10 |
| 文件頁(yè)數(shù)： | 1/3頁(yè) |
| 文件大小： | 180K |
| 代理商： | CA10 |
1
PULSEGUARD
SUPPRESSOR
SURFACE MOUNT ESD SUPPRESSORS
8-Line CA10
Obsoleted Part. Please consider PGB0010603,
PGB002ST23 or PGB0040805 for new designs.
PRODUCT OVERVIEW
PulseGuard ESD Suppressors help protect sensitive elec-
tronic equipment against electrostatic discharge (ESD).
They supplement the on-chip protection of integrated cir-
cuitry and are best suited for low-voltage, high-speed
applications where low capacitance is important.
Applications such as computer I/O ports (eg. video dis-
plays), network hardware, cell phone data ports, point-of-
sale terminals, and industrial controls will benefit
from this new technology. PulseGuard suppressors use
polymer composite materials to suppress fast-rising ESD
transients (as specified in IEC 61000-4-2 and MIL-STD-
883E).
FEATURES
Ultra-low capacitance
Low leakage current
Fast response time
Bi-directional
Withstands multiple ESD strikes
Packaged in chip array (capacitor/resistor) format
Compatible with pick-and-place processes
Available on 2,000 piece reels (EIA-RS481)
TYPICAL APPLICATIONS
Computer I/O ports (e.g. video displays)
Computer peripherals
Network hardware/ports (e.g. Gigabit Ethernet)
Point-of-Sale terminals
Cell phone data ports
Audio/video components
Test Equipment
Medical Equipment
ELECTRICAL CHARACTERISTICS
Notes:
1. 8 kV direct discharge method, per IEC 61000-4-2.
2. Measured at 1 MHz.
3. Measured at 6 VDC. Testing at fast ESD pulse rates (1-20Hz) may
cause a change in leakage current performance (6μA, max).
PHYSICAL SPECIFICATIONS
Materials:
Body: Glass Epoxy
Terminations: Tin-Lead
Soldering Parameters:
Wave solder -- 260
o
C, 10 seconds maximum
Reflow solder -- 260
o
C, 30 seconds maximum
Operating Temperature Range:
-65
o
C to +125
o
C
ORDERING INFORMATION
Catalog Number
PGB008CA10PR
Pieces per Reel
2,000
DESIGN CONSIDERATION
Because of the fast rise-time of the ESD transient, place-
ment of PulseGuard suppressors is a key design consider-
ation. To achieve optimal ESD suppression, the devices
should be placed on the circuit board as close to the
source of the ESD transient as possible. Install
PulseGuard suppressors directly behind the connector so
that they are the first board-level circuit component
encountered by the ESD transient. They are connected
from signal/data line to ground.
Trigger Voltage
1
Clamping Voltage
1
Rated Voltage
Capacitance
2
Response Time
1
Leakage Current
3
ESD Pulse Withstand
1
1,000V, typical
150V, typical
24VDC, max
0.055pF
<1ns
<1nA
1,000 pulses, minimum
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