
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Rev. 1.4
237
A wide array of digital resources is available through the four lower I/O Ports: P0, P1, P2, and P3. Each of
the pins on P0, P1, P2, and P3, can be defined as a General-Purpose I/O (GPIO) pin or can be controlled
by a digital peripheral or function (like UART0 or /INT1 for example), as shown in
Figure 18.2. The system
designer controls which digital functions are assigned pins, limited only by the number of pins available.
This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder. Note that
the state of a Port I/O pin can always be read from its associated Data register regardless of whether that
pin has been assigned to a digital peripheral or behaves as GPIO. The Port pins on Port 1 can be used as
Analog Inputs to ADC2.
An External Memory Interface which is active during the execution of an off-chip MOVX instruction can be
for more information about the External Memory Interface.
Figure 18.2. Port I/O Functional Block Diagram
External
Pins
Digital
Crossbar
Priority
Decoder
SMBus
2
SPI
4
UART0
2
PCA
2
T0, T1,
T2, T2EX,
T4,T4EX
/INT0,
/INT1
P1.0
P1.7
P2.0
P2.7
P0.0
P0.7
Highest
Priority
Lowest
Priority
8
Comptr.
Outputs
(I
nt
e
rnal
Digi
ta
l
S
igna
ls
)
Highest
Priority
Lowest
Priority
UART1
/SYSCLK divided by 1,2,4, or 8
CNVSTR0/2
7
2
P3.0
P3.7
8
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
XBR0, XBR1,
XBR2, P1MDIN
Registers
P1
I/O
Cells
P3
I/O
Cells
P0
I/O
Cells
P2
I/O
Cells
8
Port
Latches
P0
P1
P2
8
P3
8
(P2.0-P2.7)
(P1.0-P1.7)
(P0.0-P0.7)
(P3.0-P3.7)
To ADC2 Input
(‘F12x Only)
To External
Memory
Interface
(EMIF)
2