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參數(shù)資料
| 型號(hào)： | C1206N82131G4C |
| 廠商： | KEMET Corporation |
| 英文描述： | CERAMIC CHIP CAPACITORS |
| 中文描述： | 陶瓷芯片電容器 |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 2058K |
| 代理商： | C1206N82131G4C |
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KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
from that value. For example, a typical IR specification
might read
“
1,000 megohm-microfarads or 100
gigohms, whichever is less
”
. The DC leakage current
may be calculated by dividing the applied voltage by
the insulation resistance (Ohm's Law).
8.
Dielectric Withstanding Voltage:
250% of rated voltage for 5 seconds with current lim-
ited to 50mA at 25°C. Limits per Table 3.
Dielectric withstanding voltage (DWV) is the peak DC
voltage which a capacitor is designed to withstand
without damage for short periods of time. All KEMET
multilayer ceramic surface mount capacitors will with-
stand a DC test voltage of 2.5 x the rated voltage for 60
seconds.
KEMET specification limits for all electrical character-
istics at standard measurement conditions are shown in
Table 3. Variations in these properties caused by
changing conditions (temperature, voltage, frequency,
and time) are covered in the following sections.
9.
Aging Rate:
Maximum % Capacitance Loss/Decade Hour
C0G - 0%
X7R - 2.0%
X5R - 5.0%
Z5U - 7.0%
Y5V - 7.0%
Actual rates may be lower. Consult factory for
details.
The capacitance of Class II and III dielectric changes
with time as well as with temperature, voltage and fre-
quency. The change with time is known as
“
aging
”
. It is
caused by gradual realignment of the crystalline struc-
ture of the ceramic dielectric material as it is cooled
below its Curie temperature, which produces a loss of
capacitance with time. The aging process is predictable
and follows a logarithmic decay.
The aging process is reversible. If the capacitor is
heated to a temperature above its Curie point for some
period of time, de-aging will occur and the capacitor will
regain the capacitance lost during the aging process.
The amount of de-aging depends on both the elevated
temperature and the length of time at that temperature.
Exposure to 150
°
C for one-half hour is sufficient to
return the capacitor to its initial value.
Because the capacitance changes rapidly immedi-
ately after de-aging, capacitance measurements are
usually delayed for at least 24-48 hours after the de-
aging process, which is often referred to as the
“
last
heat
”
. In addition, manufacturers utilize the aging rates
to set factory test limits which will bring the capacitance
within the specified tolerance at some future time, to
allow for customer receipt and use.
10.
Effect of Temperature:
Both capacitance and dissipation factor are affected
by variations in temperature. The maximum capacitance
change with temperature is defined by the temperature
characteristic.
However, this only defines an
“
envelope
”
bounded
by the upper and lower operating temperatures and the
minimum and maximum capacitance values. Within this
“
envelope
”
, the variation with temperature depends
upon the specific dielectric formulation.
Insulation resistance decreases with increasing tem-
perature. Typically, the insulation resistance limit at
maximum rated temperature is 10% of the 25
°
C value.
11.
Effect of Voltage:
Certain high dielectric constant ceramic capacitors
may show variation in values of capacitance and dissi-
pation factor with various levels of applied AC and DC
voltages. Such variation is a natural characteristic of
ceramic capacitors, and should be considered by the
circuit designer.
In general, ceramic capacitors with the lowest dielec-
tric constant (C0G or NP0) are extremely stable, and
show little or no variation in capacitance and/or dissipa-
tion factor. On the other hand, ceramic capacitors with
the highest dielectric constant (Z5U & Y5V) may show
significant variation, particularly in capacitance. Other
dielectric formulations such as X7R and X5R will show
less variation than Y5V, but more than C0G.
The application of AC voltages in the range of 10 to
20 VAC tends to increase the values of both the capaci-
tance and dissipation factor, while higher AC voltages
tend to produce decreases in both.
However, the variation of capacitance with applied
DC is the parameter of most interest to design engi-
neers. Figure 8 shows typical variation of capacitance
with applied DC voltage for some standard dielectrics.
As can be seen, the decrease in capacitance is greatest
for the Y5V dielectric (the C0G is not plotted, since it
would not have a perceptible capacitance nor dissipa-
tion factor change.)
More detailed modelling information on the effect of
various voltages on specific capacitor ratings can be
obtained by use of the KEMET SPICE models, available
for free downloading at our website (www.kemet.com).
12.
Effect of Frequency:
Frequency affects both capacitance and dissipation
factor. Typical curves for KEMET multilayer ceramic
capacitors are shown in Figures 4, 5, 6 and 7.
The variation of impedance with frequency is an
important consideration in the application of multilayer
ceramic capacitors. Total impedance of the capacitor is
CERAMIC CHIP CAPACITORS
Figure 8 - Typical Variation of Capacitance with Applied DC Voltage
6
9
C
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