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| 型號： | BXM80532GC1600D |
| 英文描述： | Octal bus buffer with 3 state outputs (inverted) |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 17/81頁 |
| 文件大?。?/td> | 598K |
| 代理商： | BXM80532GC1600D |
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Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Order Number#249563-001
Datasheet
17
2.3
GTL+ Signals
The mobile Intel Celeron processor system bus signals use a variation of the low-voltage swing
GTL signaling technology. The mobile Intel Celeron processor system bus specification is similar
to the Pentium II processor system bus specification, which is a version of GTL with enhanced
noise margins and less ringing.
The GTL+ system bus depends on incident wave switching and uses flight time for timing
calculations of the GTL+ signals, as opposed to capacitive derating. Analog signal simulation of
the system bus including trace lengths is highly recommended. Contact your field sales
representative to receive the IBIS models for the mobile Intel Celeron processor.
The GTL+ system bus of the Celeron processor was designed to support high-speed data transfers
with multiple loads on a long bus that behaves like a transmission line. However, in mobile
systems the system bus only has two loads (the processor and the chipset) and the bus traces are
short. It is possible to change the layout and termination of the system bus to take advantage of the
mobile environment using the same GTL+ I/O buffers. In mobile systems the GTL+ system bus is
terminated at one end only. This termination is provided on the processor core (except for the
RESET# signal). Refer to the
Mobile Pentium
III
Processor GTL+ System Bus Layout Guideline
for details on laying out the GTL+ system bus.
2.4
Mobile Intel Celeron Processor CPUID
After a power-on RESET or when the CPUID version information is loaded, register EAX and
EBX[7:0] contains the values shown in Table 4. After the L2 cache is initialized, the CPUID
cache/TLB descriptors will be the values shown in Table 5.
Table 4. Mobile Intel Celeron Processor CPUID
EAX[31:0]
EBX[7:0]
Reserved [31:14]
Type [13:12]
Family [11:8]
Model [7:4]
Stepping [3:0]
Brand ID
X
0
6
8
X
01
Table 5. Mobile Intel Celeron Processor CPUID Cache and TLB Descriptors
Cache and TLB Descriptors
01H, 02H, 03H, 04H, 08H, 0CH, 41H
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