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參數(shù)資料
| 型號： | BU-65570V2-300 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, XMA |
| 封裝： | 6.3 INCH HEIGHT, VME/VXI FORMAT CARD |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 151K |
| 代理商： | BU-65570V2-300 |
6
Data Device Corporation
www.ddc-web.com
BU-65570V/65572V
F-04/05-0
the current table number will rollover to the value of first. The
incrementing of the current data table is accomplished through
the use of an intermessage routine.
MONITOR MODE
The BU-65570V/72V contains an independent message monitor
for each bus with the ability to filter messages in real time.
Monitor selection or filtering is performed through the use of a
lookup table based on the RT address, T/R bit, and sub-address
of command words. Monitored messages are stored in the
shared RAM on the BU-65570V/72V. Each entry in the monitor
buffer contains a header followed by a variable number of data
words. Contained with the message header are the
receive/transmit command(s), receive/transmit status, message
format, Bus (A or B), a capture flag, word count (actual number
of words in the message), a detected error field, and a 32-bit
time tag (1 μsec resolution).
The transfer of the messages from the card's circular buffer to
the host memory/disk is determined by the capture flag, which is
set upon detection of a predefined event. Capture events include
immediate, command template match, exception, or trigger. The
command template event is based on a 16-bit command word
with a 16-bit mask. Exception events may be programmed for
any exception: invalid command, invalid data, invalid status, gap
preceding data, response time error, wrong RT address error,
status set condition or an illegal command. The trigger event
uses one of the four monitor input pins on the 9-pin D-type con-
nector as a trigger input.
DMA transfers are possible using the PCI Master Mode. The
Monitor mode can autonomously transfer monitored data to RAM
in PCI address space without host CPU intervention. This greatly
improves the efficiency of both the host and the BU-65570V/72V.
INTERRUPTS
For each of the installed channels, both the BC/RT and the
Monitor may request interrupts on a common output to the PCI
back plane. The hardware interrupt level used by the BU-
65570V/72V is selected by the Plug-and-Play capability of the
PCI back plane and BIOS. An important aspect of PCI interrupts
is that they are sharable. This means that the BU-65570V/72V
can share an interrupt for all buses on the card.
BC INTERRUPT GENERATION
BC interrupts may be enabled by a global interrupt mask for suc-
cessful messages, communication errors, status set conditions,
or on selected frame symbols (skip, break point, major frame,
and minor frame symbols). The criteria for a status set condition
are programmed globally through the use of a status mask. The
status mask allows any of the 16 bits within the RT status word
to be ignored. The status mask affects the generation of inter-
rupts as well as the detected error field that is stored in the mes-
sage structure.
BC interrupts are issued by the intermessage routines associat-
ed with messages allowing for selective interrupt generation on
a message by message basis. A two-word vector is pushed onto
a circular queue for each interrupt request and is transparent to
the user. The queue can hold up to 64 interrupt vectors; thus, the
host computer is not required to immediately acknowledge the
interrupt request.
TABLE 6. BC/RT INTERMESSAGE ROUTINES
INTERRUPT ON FRAME SYMBOL *
SKIP NEXT MESSAGE *
SKIP NEXT MESSAGE ONCE *
BLOCK_DATA_BC *
NO OPERATION
BLOCK_DATA_RT **
RETRY CURRENT MESSAGE ON ALTERNATE BUS *
SET_DISCRETE_0
RESET_DISCRETE_0
SET_DISCRETE_1
RETRY ON SAME BUS *
SET SERVICE REQUEST BIT IN STATUS **
RESET_DISCRETE_1
RESET SERVICE REQUEST BIT IN STATUS **
SET_DISCRETE_2
INTERRUPT AFTER ACCESSING TX/RX DATA TABLE
RESET_DISCRETE_2
INTERRUPT AFTER MODE COMMAND **
RESET_DISCRETE_3
INTERRUPT AFTER TX/RX COMMAND TEMPLATE MATCH **
SET_DISCRETE_3
INTERRUPT AFTER MODE COMMAND TEMPLATE MATCH **
TIME-TAG (STORE RTC IN A CIRCULAR QUEUE)
RETRY ON SAME BUS AND THEN ON ALTERNATE BUS *
SET OUTPUT TRIGGER
WAIT FOR INPUT TRIGGER *
NO RESPONSE ON BOTH BUSES **
SET BUSY BIT IN STATUS **
RESET BUSY BIT IN STATUS **
RETRY CURRENT MESSAGE AND REMAIN ON ALTERNATE BUS *
INTERRUPT ON END OF MESSAGE
* Applicable to BC only.
** Applicable to RT only.
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