參數(shù)資料
型號(hào)： BU-62864B3-142S
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
封裝： 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128
文件頁數(shù)： 8/93頁
文件大?。?/td> 504K
代理商： BU-62864B3-142S
Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
16
FAILSAFE INTERRUPT ENABLE: When set to a “1”, an interrupt is generated if
not in FAILSAFE OFF mode and a FAILSAFE error is detected.
FAILSAFE INTERRUPT AUTOCLEAR ENABLE: If set, causes interrupt and the
FAIL_SAFE ERROR bit (REG0-bit 22) to be cleared whenever upper word of
REG0 is read by the PCI MASTER.
FAILSAFE MODE: Fail Safe Errors occur when either the ACE or the Local
Processor fail to assert a hand-shake signal (e.g. ACE Ready or Bus Grant)
within 1 millisecond (programmable) of when the Strobe or Request signal is
asserted. Four possible FAILSAFE Modes determine how this situation is
handled:
Table 8. FAILSAFE MODE
BIT 17
BIT 16
FAILSAFE MODE
0
FailSafe Off
0
1
FailSafe Retry
1
0
FailSafe Halt
1
FailSafe Skip
MODE 1 - FAILSAFE OFF. PCI Enhanced Mini-ACE will wait indefinitely for the
transaction to complete. The local bus could hang as a result. The FAILSAFE
ERROR bit and interrupt will not be generated even if the enable bit is set.
MODE 2 - FAILSAFE RETRY. PCI Enhanced Mini-ACE will retry the transfer on
the local bus when the FAILSAFE timer times out.
MODE 3 - FAILSAFE HALT. Once the FAILSAFE timer times out, all future
transfers will be terminated with a target abort until the PCI master clears the
interrupt.
MODE 4 - FAILSAFE SKIP. Once the FAILSAFE timer times out, the current
transaction is discarded or skipped and the next transaction, whether a stored
write in the FIFO or a new transaction, will be attempted.
INTERRUPT VECTOR FROM PCI: Writing to this location by the PCI Master
causes a local processor interrupt only if at least one of the bits (15-0) is a ‘1’.
Reading this location by the local processor clears the register. The PCI Master
may read back this register to determine if the local processor has read it yet and
will not cause it to clear.
Subsequent writes occurring to this register by the PCI Master prior to a local
processor read can set new bits in the register. Any bits previously set cannot be
cleared by new writes. Bits in this register can only be cleared by a local
processor read.
相關(guān)PDF資料
PDF描述
BU-62864B4-150 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
BU-65142D2-110W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142D2-140W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78
BU-65142F2-190W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP78
BU-65170S3-202 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP70
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