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| 型號(hào)： | BU-62843B4-170Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128 |
| 封裝： | 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128 |
| 文件頁(yè)數(shù)： | 7/93頁(yè) |
| 文件大?。?/td> | 504K |
| 代理商： | BU-62843B4-170Q |
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Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
15
Table 7. REG1 Fail-Safe Operation / Interrupt Register
(Read/Write 804h)
BIT
DESCRIPTION
31 (MSB)
DRR_HOLD
30
VECTOR_IRQ_DISABLE
29
SETUP DELAY FOR LOCAL BUS – BIT 1 (MSB)
28
SETUP DELAY FOR LOCAL BUS – BIT 0 (LSB)
27
LOCAL PROCESSOR INTERRUPT ENABLE
26
0
25
0
24
0
23
0
22
0
21
PCI ENHANCED MINI-ACE INTERRUPT ENABLE
20
BAR1 DRR_DATA_DISCARD INTERRUPT ENABLE
19
FAILSAFE INTERRUPT ENABLE
18
FAILSAFE INTERRUPT AUTOCLEAR ENABLE
17
FAILSAFE MODE - BIT 1 (MSB)
16
FAILSAFE MODE - BIT 0 (LSB)
15
INTERRUPT VECTOR FROM PCI - BIT 15 (MSB)
0 (LSB)
INTERRUPT VECTOR FROM PCI - BIT 0 (LSB)
DRR_HOLD: When ‘0’, a delayed read request is discarded if PCI Enhanced
Mini-ACE has obtained requested data and a different transaction is requested.
When ‘1’, delayed read request is held until master repeats original request or
timeout occurs.
VECTOR_IRQ_DISABLE: When ‘0’, the 16 bits of interrupt field act as a vector.
All 16 bits are written to ‘0’ or ‘1’ corresponding to the input data of the current
write operation. When ‘1’, the interrupt no longer acts as a vector. Once a bit in
the 16 bit interrupt field is set to ‘1’, it cannot be written back to ‘0’. Bits are
cleared only upon a read by the interrupt recipient.
SETUP DELAY FOR LOCAL BUS:
00 – (default) Data setup 1 clock prior to write pulse on local bus.
01 – Data set up 2 clocks prior to write pulse on local bus.
10 – Data set up 3 clocks prior to write pulse on local bus.
11 – Data set up 4 clocks prior to write pulse on local bus.
PCI ENHANCED MINI-ACE INTERRUPT ENABLE: Must be set to “1”.
BAR1 DRR_DATA_DISCARD INTERRUPT ENABLE: Enables interrupt to occur
on a BAR1 delayed read timeout.
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