參數(shù)資料
型號(hào)： BU-62843B3-120
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, BGA128
封裝： 0.815 X 0.815 INCH, 0.140 INCH HEIGHT, 1 MM PITCH, BGA-128
文件頁數(shù)： 6/93頁
文件大?。?/td> 504K
代理商： BU-62843B3-120
Data Device Corporation
62743_pre2.DOC
www.ddc-web.com
8-15-01
14
Table 6. REG0 Global Activity Register
(Read 800h)
BIT
DESCRIPTION
31 (MSB)
PCI INTERRUPT ACTIVE
30
FIFO NOT EMPTY
29
PCI_TEST
28
LOCAL CPU PRESENT
27
0
26
0
25
0
24
1
23
BAR1 DRR_DATA_DISCARD
22
FAIL_SAFE ERROR
21
0
20
0
19
0
18
0
17
0
16
PCI ENHANCED MINI-ACE INTERRUPT ACTIVE
15
INTERRUPT VECTOR TO PCI - BIT 15 (MSB)
0 (LSB)
INTERRUPT VECTOR TO PCI - BIT 0 (LSB)
PCI_TEST: When set to ‘1’, in PCI_TEST mode causes short boot.
LOCAL CPU PRESENT: When set to ‘1’, a local CPU has been detected.
BAR1 DRR_DATA_DISCARD: If the data discard timer times out while waiting
for a retry on a BAR1 access, this bit will be set. If BAR1 read is discarded, it
may have caused an action (for example clearing an ACE interrupt) that has not
been recognized by the PCI MASTER.
FAIL SAFE ERROR: If not in FAIL_SAFE OFF mode and fail safe error occurs
(local CPU or ACE does not respond), this bit will be set.
INTERRUPT VECTOR TO PCI: Writing to this location by the local processor
causes a PCI interrupt if at least one of the bits (15-0) is a ‘1’. Reading this
location from the PCI bus clears the register. Can be read by local processor to
see if PCI master has read it yet and will not cause it to clear.
Subsequent writes occurring to this register by the local processor prior to a PCI
Master read can set new bits in the register. Any bits previously set cannot be
cleared by new writes. Bits in this register can only be cleared by a PCI Master
read.
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