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| 型號(hào)： | BU-61585G3-190K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70 |
| 封裝： | GULLWING PACKAGE-70 |
| 文件頁(yè)數(shù)： | 13/44頁(yè) |
| 文件大?。?/td> | 563K |
| 代理商： | BU-61585G3-190K |
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20
Data Device Corporation
www.ddc-web.com
BU-65170/61580/61585
H1 web-09/02-0
BU-65170 or BU-61580 to a host processor bus. The various
possible configurations serve to reduce to an absolute minimum
the amount of glue logic required to interface to 8-, 16-, and 32-
bit processor buses. Also included are features to facilitate inter-
facing to processors that do not have a “wait state” type of hand-
shake acknowledgement. Finally, the ACE supports a reliable
interface to an external dual port RAM. This type of interface
minimizes the portion of the available processor bandwidth
required to access the 1553 RAM.
The 16-bit buffered mode (FIGURE 9) is the most common con-
figuration used. It provides a direct, shared RAM interface to a
16-bit or 32-bit microprocessor. In this mode, the ACE's internal
address and data buffers provide the necessary isolation
between the host processor's address and data buses and the
corresponding internal memory buses. In the buffered mode, the
1553 shared RAM address space limit is the BU-65170/61580's
4K words of internal RAM. The 16-bit buffered mode provides a
pair of pin-programmable options:
(1) The logic sense of the RD/WR control input is selectable
by the POLARITY_SEL input: For example, write when
RD/WR is low for Motorola 680X0 processors; write when
RD/WR is high for the Intel i960 series microprocessors.
(2) By strapping the input signal ZERO_WAIT to logic "1,"
the ACE terminals may interface to processors that have an
acknowledge type of handshake input to accommodate
hardware controlled wait states; most current processor
chips have such an input. In this case, the BU-65170/61580
will assert its READYD output low only after it has latched
WRITE data internally or has presented READ data on D15-
D0.
By strapping ZERO_WAIT to logic "0," it is possible to easily
interface the BU-65170/61580 to processors that do not have an
acknowledge type of handshake input. An example of such a
processor is Analog Device's ADSP2101 DSP chip. In this con-
figuration, the processor can clear its strobe output before the
completion of access to the BU-65170/61580 internal RAM or
register. In this case, READYD will go high following the rising
edge of STRBD and will stay high until completion of the trans-
fer. READYD will normally be low when ZERO_WAIT is low.
Similar to the 16-bit buffered mode, the 16-bit transparent mode
(FIGURE 10) supports a shared RAM interface to a host CPU.
The transparent mode offers the advantage of allowing the
buffer RAM size to be expanded to up to 64K words, using exter-
nal RAM. A disadvantage of the transparent mode is that it
requires external address and data buffers to isolate the proces-
sor buses from the memory/BU-65170/61580 buses.
A modified version of the transparent mode involves the use of
dual port RAM, rather than conventional static RAM. Refer to
FIGURE 11. This allows the host to access RAM very quickly,
the only limitation being the access time of the dual port RAM.
This configuration eliminates the BU-65170/61580 arbitration
delays for memory accesses. The worst case delay time occurs
only during a simultaneous access by the host and the BU-
65170/61580 1553 logic to the same memory address. In gen-
eral, this will occur very rarely and the ACE limits the delay to
approximately 250 ns.
FIGURE 12 illustrates the connections for the 16-bit Direct
Memory Access (DMA) mode. In this configuration the host
processor, rather than the ACE terminal, arbitrates the use of the
address and data buses. The arbitration involves the two DMA
output signals Request (DTREQ) and Acknowledge (DTACK),
and the input signal Grant (DTGRT). The DMA interface allows
the ACE components to interface to large amounts of system
RAM while eliminating the need for external buffers. For system
address spaces larger than 64K words, it is necessary for the
host processor to provide a page register for the upper address
bits (above A15) when the BU-65170/61580 accesses the RAM
(while asserting DTACK low).
The internal RAM is accessible through the standard ACE inter-
face (SELECT, STRBD, READYD, etc). The host CPU may
access external RAM by the ACE's arbitration logic and output
control signals, as illustrated in FIGURE 12. Alternatively, control
of the RAM may be shared by both the host processor and the
ACE, as illustrated in FIGURE 13. The latter requires the use of
external logic, but allows the processor to access the RAM
directly at the full access speed of the RAM, rather than waiting
for the ACE handshake acknowledge output (READYD).
FIGURE 14 illustrates the 8-bit buffered mode. This interface
allows a direct connection to 8-bit microprocessors and 8-bit
microcontrollers. As in the 16-bit buffered configuration, the
buffer RAM limit is the BU-65170/61580's 4K words of internal
RAM. In the 8-bit mode, the host CPU accesses the BU-
65170/61580's internal registers and RAM by a pair of 8-bit reg-
isters embedded in the ACE interface. The 8-bit interface may be
further configured by three strappable inputs: ZERO_WAIT,
POLARITY_SEL,
and
TRIGGER_SEL.
By
connecting
ZERO_WAIT to logic "0," the BU-65170/61580 may be interfaced
with minimal "glue" logic to 8-bit microcontrollers, such as the
Intel 8051 series, that do not have an Acknowledge type of hand-
shake input. The programmable inputs POLARITY_SEL and
TRIGGER_SEL allow the BU-65170/61580 to accommodate the
different byte ordering conventions and "A0" logic sense utilized
by different 8-bit processor families.
PROCESSOR INTERFACE TIMING
FIGURES 15 and 16 illustrate the timing for the host processor
to access the ACE's internal RAM or registers in the 16-bit,
buffered, non-zero, wait-mode. FIGURE 15 illustrates the 16-bit
buffered, nonzero wait mode read cycle timing while FIGURE 16
shows the 16-bit, buffered, nonzero wait mode write cycle timing.
During a CPU transfer cycle, the signals STRBD and SELECT
must be sampled low on the rising edge of the system clock to
request access to the BU-65170/61580's internal shared RAM.
The transfer will begin on the first rising system clock edge when
(SELECT and STRBD) is low and the 1553 protocol/memory
management unit is not accessing the internal RAM. The falling
edge of the output signal IOEN indicates the start of the transfer.
The ACE latches the signals MEM/REG and RD/WR internally
on the first falling clock edge after the start of the transfer cycle.
The address inputs latch internally on the first rising clock edge
after the signal IOEN goes low. Note that the address lines may
be latched at any time using the ADDR_LAT input signal.
The output signal READYD will be asserted low on the third ris-
ing system clock edge after IOEN goes low. The assertion of
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