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參數(shù)資料
| 型號(hào)： | BU-61582G2-841 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CDSO70 |
| 封裝： | CERAMIC PACKAGE-70 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 78K |
| 代理商： | BU-61582G2-841 |
NOW
MEETS
1 MRAD
!
DESCRIPTION
DDC’s BU-61582 Space Advanced
Communication Engine (SP’ACE) is a
radiation hardened version of the BU-
61580 ACE terminal. DDC is able to
supply the BU-61582 with enhanced
screening for space and other high
reliability applications.
The BU-61582 provides a complete
integrated
BC/RT/MT
interface
between a host processor and a MIL-
STD-1553 bus. The BU-61582 pro-
vides functional and software compat-
ibility with the standard BU-61580
product and is packaged in the same
1.9-square-inch package footprint.
As an option, DDC can supply the
BU-61582 with space level screening.
This entails enhancements in the
areas of element evaluation and
screening procedures for active and
passive elements, as well as the man-
ufacturing and screening processes
used in producing the terminals.
The BU-61582 integrates dual trans-
ceiver, protocol, memory manage-
ment and processor interface logic,
and 16K words of RAM in the choice
of 70-pin DIP or flat pack packages.
Transceiverless versions may be
used with an external electrical or
fiber optic transceiver.
To minimize board space and ‘glue’
logic, the SP’ACE terminals provide
ultimate flexibility in interfacing to a
host processor and internal/external
RAM.
SPACE LEVEL MIL-STD-1553 BC/RT/MT
ADVANCED COMMUNICATION ENGINE
FEATURES
Radiation-Hardened to 1 MRad
Fully Integrated 1553 Terminal
Flexible Processor Interface
16K x 16 Internal RAM
Automatic BC Retries
Programmable BC Gap Times
BC Frame Auto-Repeat
Intelligent RT Data Buffering
Small Ceramic Package
Available to SMD 5962-96887
TRANSCEIVER
A
CH. A
TRANSCEIVER
B
CH. B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
RT ADDRESS
16KX16
SHARED
RAM
ADDRESS BUS
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
DATA BUS
D15-D0
A15-A0
DATA
BUFFERS
ADDRESS
BUFFERS
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
MISCELLANEOUS
INCMD
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
RTAD4-RTAD0, RTADP
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
FIGURE 1. BU-61582 BLOCK DIAGRAM
ACE User’s Guide
Also Available
BU-61582
1995, 1999 Data Device Corporation
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| BU-61585 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |ACE |
| BU-61586 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |ACE |
| BU61586V6-300 | 制造商:DDC 功能描述:MIL-STD-1553/ARINC BUS CONTROLLER/RTU, 70 Pin, Flat Pack |
| BU-61588 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
| BU-61588F0 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MINIATURE ADVANCED COMMUNICATION ENGINE (MINI-ACE) AND MINI-ACE PLUS |
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