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參數(shù)資料
| 型號： | BU-61580V6-200 |
| 英文描述： | MIL-STD-1553/ARINC Bus Controller/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大小： | 833K |
| 代理商： | BU-61580V6-200 |
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6
Data Device Corporation
www.ddc-web.com
BU-61559 Series
C-12/02-300
INTERNAL REGISTERS, MEMORY MANAGEMENT,
AND INTERRUPTS
The software interface of the BU-61559 to the host processor
consists of eight internal registers plus 64K X 16 of shared mem-
ory address space. The BU-61559's 8K X 16 of internal RAM
resides in this address space.
The address mapping and accessibility for the eight registers is
defined as follows:
ADDRESS LINES
A2
A0
A1
0
0
Interrupt Mask Register (RD/WR)
0
0
1
Configuration Register # 1 (RD/WR)
0
0
0
Configuration Register # 2 (RD/WR)
1
0
1
Start/Reset Register (WR)
1
0
1
Stack Pointer Register (RD)
1
1
0
Subaddress Control Word Register (RD/WR)
0
1
1
Time Tag Register (RD/WR)
0
1
0
Interrupt Status Register (RD)
1
1
1
RESERVED
1
REGISTER
DESCRIPTION/ACCESSIBILITY
The Interrupt Mask Register is used to enable and disable inter-
rupt requests for various conditions. Configuration Registers #1
and #2 are used to select the BU-61559's mode of operation as
well as for software control of RT Status Word bits, Active
Memory Area, BC Stop-on-Error, RT Memory Management
mode selection, and other functions involving the Service
Request Status bit, interrupts, and resolution and operation of
the Time Tag Register.
The Start/Reset Register is used for “command” type functions,
such as software reset and BC/MT Start as well as Interrupt
Reset, Time Tag Reset, and Time Tag Register Test. The Stack
Pointer Register allows the host CPU to determine the pointer
location for the current or most recent message when the BU-
61559 is in BC or RT modes.
The Subaddress Control Word Register allows the host proces-
sor access to the current or most recent Subaddress Control
Word; the read/write accessibility of this register can be used to
facilitate the testing of the BU-61559.
The 16-bit Time Tag Register maintains the value of a real time
clock. The resolution of this register is programmable from
among 2, 4, 8, 16, 32, and 64 μs/LSB. The Time Tag Register
may also be clocked from an external oscillator. The current
value of the Time Tag Register is written to the stack area of
RAM during Start-of-Message (SOM) and End-of-Message
(EOM) sequences in BC and RT modes.
The Interrupt Status Register mirrors the Interrupt Mask Register
and contains a Master Interrupt bit. It allows the host processor
to determine the cause of an interrupt request by means of a sin-
gle READ operation.
The bit maps of the eight registers are defined in FIGURES 2
and 3.
BLOCK STATUS WORD
The Block Status Word is stored in the first location of the
Message Block descriptor in the Stack area of the shared RAM
for both BC and RT modes. It is updated by the 1553 memory
management logic both at the beginning and at the end of the
respective message. It contains information relating to whether
the message is in progress or has been completed, what chan-
nel it was processed on, and whether or not there were any
errors in the message.
FIGURE 2. INTERRUPT MASK REGISTER
FIGURE 3. CONFIGURATION REGISTER #1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61580V6-300 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581 | MIL-STD-1553 Components |ACE |
| BU-61581G1-100 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581S3-122 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581S6-100 | MIL-STD-1553/ARINC Bus Controller/RTU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61580V6-300 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |ACE |
| BU61581F6-300 | 制造商:DDC 功能描述:61581F6-300 |
| BU-61581G1-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581G1-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
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