- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369517 > BT848A Single-Chip Video Capture for PCI PDF資料下載
參數(shù)資料
| 型號(hào)： | BT848A |
| 英文描述： | Single-Chip Video Capture for PCI |
| 中文描述： | 單芯片的PCI視頻捕捉 |
| 文件頁(yè)數(shù)： | 85/141頁(yè) |
| 文件大小： | 1149K |
| 代理商： | BT848A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)當(dāng)前第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)
Brooktree
75
L848A_A
E
LECTRICAL
I
NTERFACES
I
2
C Interface
Bt848/848A/849A
Single-Chip Video Capture for PCI
I
2
C Interface
The Inter-Integrated Circuit (I
2
C) bus is a two-wire serial interface. Serial clock
and data lines, SCL and SDA, are used to transfer data between the bus master and
the slave device.
The Bt848 implements a single master I
2
C system, allowing no other I
2
C mas-
ter devices, but many slaves may be in the system. The timing for the bus will be
derived from the PCI clock which may be 33 MHz or slower. Bt848’s fixed divide
by 16 divider provides a timing resolution of 0.48
μ
S. A programmable register de-
termines the additional divide ratio to divide the clock down to 100 KHz or slower
rates. The formula for the I
2
C bit rate is as follows:
An I
2
C slave may slow down the data transfer rate even further by inserting wait
states.
The relationship between SCL and SDA is decoded to provide both a start and
stop condition on the bus. To initiate a transfer on the I
2
C bus, the master must
transmit a start pulse to the slave device. This is accomplished by taking the SDA
line low while the SCL line is held high. The master should only generate a start
pulse at the beginning of the cycle, or after the transfer of a data byte to or from the
slave. To terminate a transfer, the master must take the SDA line high while the
SCL line is held high. The master may issue a stop pulse at any time during an I
2
C
cycle. Since the I
2
C bus will interpret any transition on the SDA line during the
high phase of the SCL line as a start or stop pulse, care must be taken to ensure that
data is stable during the high phase of the clock. This is illustrated in Figure 35.
Bit Rate
16
I2CDIV
×
(
4
4
+
)
×
---------PCI Clock Rate
=
where:
I2CDIV
= Register bits in the I
2
C Data/Control Register
Figure 35. The Relationship between SCL and SDA
S
TART
S
TOP
SDA
SCL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BT849A | Single-Chip Video Capture for PCI |
| BT8510EPJC | PCM Transceiver |
| BT857KPJ | Color Encoder Circuit |
| BT8958EHJ50 | xDSL Interface |
| BT8953AEPFC | xDSL Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BT848AKPF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Video Capture for PCI |
| BT848KPF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Video Capture for PCI |
| BT849A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Video Capture for PCI |
| BT849AKPF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Video Capture for PCI |
| BT850-SA | 功能描述:BTV4.2 DUAL MODE USB HCI MODULE 制造商:laird - wireless & thermal systems 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。