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參數(shù)資料
| 型號： | BST100 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 小信號晶體管 |
| 英文描述： | P-channel enhancement mode vertical D-MOS transistors(P溝道增強型垂直D-MOS晶體管) |
| 中文描述： | 300 mA, 60 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET, TO-92 |
| 封裝： | PLASTIC, SOT-54 (TO-92) VARIANT, 3 PIN |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 67K |
| 代理商： | BST100 |
April 1995
4
Philips Semiconductors
Product specification
P-channel enhancement mode vertical
D-MOS transistor
BST100
CHARACTERISTICS
T
j
= 25
°
C unless otherwise specified
Drain-source breakdown voltage
I
D
= 10
μ
A; V
GS
= 0
Drain-source leakage current
V
DS
= 48 V; V
GS
= 0
Gate-source leakage current
V
GS
= 20 V; V
DS
= 0
Gate threshold voltage
I
D
= 1 mA; V
DS
= V
GS
V
(BR)DSS
min.
60 V
I
DSS
max.
1
μ
A
I
GSS
max.
100 nA
min.
max.
1.5
3.5
V
V
V
GS(th)
Drain-source ON-resistance
I
D
= 200 mA;
V
GS
= 10 V
typ.
max.
4.5
6
R
DS(on)
Transfer admittance
I
D
= 200 mA;
V
DS
= 15 V
Input capacitance at f = 1 MHz
V
DS
= 10 V; V
GS
= 0
Y
fs
typ.
200 mS
typ.
max.
55
70
pF
pF
C
iss
Output capacitance at f = 1 MHz
V
DS
= 10 V; V
GS
= 0
typ.
max.
30
45
pF
pF
C
oss
Feedback capacitance at f = 1 MHz
V
DS
= 10 V; V
GS
= 0
typ.
max.
8
12
pF
pF
C
rss
Switching times (see Figs 2 and 3)
I
D
= 200 mA;
V
DD
= 50 V;
V
GS
= 0 to 10 V
t
on
t
off
typ.
typ.
4
20
ns
ns
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