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參數(shù)資料
| 型號(hào)： | BSR58LT1 |
| 元件分類： | TVS-瞬態(tài)抑制二極管 |
| 英文描述： | Transient Voltage Suppressor Diodes |
| 中文描述： | 晶體管|場(chǎng)效應(yīng)| N溝道| 8mA的我（直）| SOT - 23封裝 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | BSR58LT1 |
BSR58LT1
http://onsemi.com
2
t
t
t
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0
2.0
3.0
5.0 7.0
10
20
30
50
I
D
, DRAIN CURRENT (mA)
Figure 1. Turn–On Delay Time
R
K
= 0
T
J
= 25
°
C
J111
J112
J113
V
GS(off)
= 12 V
= 7.0 V
= 5.0 V
R
K
= R
D
′
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0
2.0
3.0
5.0 7.0
10
20
30
50
I
D
, DRAIN CURRENT (mA)
Figure 2. Rise Time
R
K
= R
D
′
R
K
= 0
T
J
= 25
°
C
J111
J112
J113
V
GS(off)
= 12 V
= 7.0 V
= 5.0 V
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0
2.0
3.0
5.0 7.0
10
20
30
50
I
D
, DRAIN CURRENT (mA)
Figure 3. Turn–Off Delay Time
R
K
= R
D
′
R
K
= 0
T
J
= 25
°
C
J111
J112
J113
V
GS(off)
= 12 V
= 7.0 V
= 5.0 V
t
1000
1.0
2.0
5.0
10
20
50
100
200
500
0.5 0.7 1.0
2.0
3.0
5.0 7.0
10
20
30
50
I
D
, DRAIN CURRENT (mA)
Figure 4. Fall Time
R
K
= R
D
′
R
K
= 0
T
J
= 25
°
C
J111
J112
J113
V
GS(off)
= 12 V
= 7.0 V
= 5.0 V
TYPICAL SWITCHING CHARACTERISTICS
NOTE 1
The switching characteristics shown above were measured using a test cir-
cuit similar to Figure 5. At the beginning of the switching interval, the gate
voltage is at Gate Supply Voltage (–V
GG
). The Drain–Source Voltage
(V
DS
) is slightly lower than Drain Supply Voltage (V
DD
) due to the voltage
divider. Thus Reverse Transfer Capacitance (C
rss
) or Gate–Drain Capaci-
tance (C
gd
) is charged to V
GG
+ V
DS
.
During the turn–on interval, Gate–Source Capacitance (C
gs
) discharges
through the series combination of R
Gen
and R
K
. C
gd
must discharge to
V
DS(on)
through R
G
and R
K
in series with the parallel combination of ef-
fective load impedance (R
′
D
) and Drain–Source Resistance (r
ds
). During
the turn–off, this charge flow is reversed.
Predicting turn–on time is somewhat difficult as the channel resistance
r
ds
is a function of the gate–source voltage. While C
gs
discharges, V
GS
ap-
proaches zero and r
ds
decreases. Since C
gd
discharges through r
ds
, turn–on
time is non–linear. During turn–off, the situation is reversed with r
ds
in-
creasing as C
gd
charges.
The above switching curves show two impedance conditions; 1) R
K
is
equal to R
D
, which simulates the switching behavior of cascaded stages
where the driving source impedance is normally the load impedance of the
previous stage, and 2) R
K
= 0 (low impedance) the driving source imped-
ance is that of the generator.
R
GEN
50
V
GEN
INPUT
R
K
50
R
GG
V
GG
50
OUTPUT
R
D
+V
DD
R
T
SET V
DS(off)
= 10 V
INPUT PULSE
t
r
t
f
PULSE WIDTH
DUTY CYCLE
0.25 ns
≤
0.5 ns
= 2.0
μ
s
≤
2.0%
R
GG
R
K
RD
RD(RT
RD
50)
RT
50
Figure 5. Switching Time Test Circuit
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