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參數(shù)資料
| 型號(hào)： | BH7881EFV-E2 |
| 廠商： | Rohm Semiconductor |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP HDPH/SPEAKER LV 24HTSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | AB 類 |
| 輸出類型： | 2 通道（立體聲） |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 2W x 2 @ 4 歐姆 |
| 電源電壓： | 3.3 V ~ 5.5 V |
| 特點(diǎn)： | 低音增強(qiáng)模式，靜音，短路和熱保護(hù)，待機(jī) |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 24-HTSSOP-B |
| 封裝/外殼： | 24-VSSOP（0.220"，5.60mm 寬）裸露焊盤 |
| 包裝： | 帶卷 (TR) |
5
SY88983V
Micrel, Inc.
M9999-020205
hbwhelp@micrel.com or (408) 955-1690
February 2005
DETAILED DESCRIPTION
The SY88983V low power limiting post amplifier operates
from a single +3.3V or +5V power supply, over temperatures
from –40
°C to +85°C. Signals with data rates up to 3.2Gbps
and as small as 10mVp-p can be amplified. Figure 1 shows
the allowed input voltage swing. The SY88983V generates
an SD output, allowing feedback to EN for output stability.
SD
LVL sets the sensitivity of the input amplitude detection.
Input Amplifier/Buffer
The SY88983V’s inputs are internally terminated with 50
to V
REF. Unless they are not affected by this internal
termination scheme, upstream devices need to be
AC-coupled to the SY88983V’s inputs. Figure 2 shows a
simplified schematic of the input stage.
The high sensitivity of the input amplifier allows signals
as small as 10mVp-p to be detected and amplified. The
input amplifier allows input signals as large as 1800mVp-p.
Input signals are linearly amplified with a typically 38dB
differential voltage gain. Since it is a limiting amplifier, the
SY88983V outputs typically 800mVp-p voltage-limited
waveforms for input signals that are greater than 10mVp-p.
Applications requiring the SY88983V to operate with high-
gain should have the upstream TIA placed as close as
possible to the SY88983V’s input pins to ensure the best
performance of the device.
Output Buffer
The SY88983V’s CML output buffer is designed to drive
50
lines. The output buffer requires appropriate termination
for proper operation. An external 50
resistor to V
CC or
equivalent for each output pin provides this. Figure 3 shows
a simplified schematic of the output stage and includes an
appropriate termination method. Of course, driving a
downstream device with a CML input that is internally
terminated with 50
to V
CC eliminates the need for external
termination. As noted in the previous section, the amplifier
outputs typically 800mVp-p waveforms across 25 total
loads. The output buffer, thus, switches typically 16mA tail-
current. Figure 4 shows the power supply current
measurement, which excludes the 16mA tail-current.
Signal Detect
The SY88983V generates a chatter-free signal detect
(SD) open-collector TTL output with internal 5k
pull-up
resistor as shown in Figure 5. SD is used to determine that
the input amplitude is large enough to be considered a
valid input. SD asserts high if the input amplitude rises
above the threshold set by SD
LVL and de-asserts low
otherwise. SD can be fed back to the enable (EN) input to
maintain output stability under a loss-of-signal condition.
EN de-asserts low the true output signal without removing
the input signals. Typically, 4.6dB SD hysteresis is provided
to prevent chattering.
Signal Detect-Level Set
A programmable signal detect-level set pin (SD
LVL) sets
the threshold of the input amplitude detection. Connecting
an external resistor between V
CC and SDLVL sets the voltage
at SD
LVL. This voltage ranges from VCC to VREF. The
external resistor creates a voltage divider between V
CC and
V
REF as shown in Figure 6. If desired, an appropriate
external voltage may be applied rather than using a resistor.
The smaller the external resistor, implying a smaller voltage
difference from SD
LVL to VCC, lowers the SD sensitivity.
Hence, larger input amplitude is required to assert SD.
“Typical Operating Characteristics” shows the relationship
between the input amplitude detection sensitivity and the
SD
LVL setting resistor.
Hysteresis
The SY88983V provides typically 4.6dB SD electrical
hysteresis. By definition, a power ratio measured in dB is
10log(power ratio). Power is calculated as V2
IN/R for an
electrical signal. Hence, the same ratio can be stated as
20log(voltage ratio). While in linear mode, the electrical
voltage input changes linearly with the optical power and
hence, the ratios also change linearly. Therefore, the optical
hysteresis in dB is half the electrical hysteresis in dB given
in the data sheet. The SY88983V provides typically 2.3dB
SD optical hysteresis. As the SY88983V is an electrical
device, this data sheet refers to hysteresis in electrical terms.
With 4.6dB SD hysteresis, a voltage factor of 1.7 is required
to assert SD from its de-assert value.
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