參數(shù)資料
型號(hào): BD4PUODF5FSLS33
英文描述: Triac; Triac Type:Alternistor; Peak Repetitive Off-State Voltage, Vdrm:400V; On-State RMS Current, IT(rms):6A; Gate Trigger Current (QI), Igt:35mA; Package/Case:3-TO-220; Current, It av:6A; Gate Trigger Current Max, Igt:35mA
中文描述: 緩沖器/驅(qū)動(dòng)器
文件頁(yè)數(shù): 8/12頁(yè)
文件大?。?/td> 135K
代理商: BD4PUODF5FSLS33
8
G12-p 3.3 V, 4 mA, 5-Volt Tolerant, Fail-Safe, General Purpose I/O Buffers
Driver Slew Rate
The following slew rate measurement applies to the
bd4f5fsls33
and
bd4puf5fsls33
buffers in totem-pole mode. In the rise/fall test, the driver
drives a signal across a 40 pF load capacitor (
Figure 2
).
Table 8
shows
the observed slew rate across the load capacitor measured from 0.6 V
to 2.2 V.
Figure 2
Rise/Fall Test Circuit
Testing
The buffers include test circuitry and signals compatible with standard
LSI Logic test methodology. The PI and PO NAND-tree signals provide
access for parametric testing. The global IDDTN signal powers down all
circuitry for IDDQ leakage testing.
IMPORTANT:
The IDDQ leakage test requires the I/O buffers in the high-
impedance state. Setting IDDTN to LOW usually accom-
plishes this condition. However, with the I/O buffers that use
CEN to preset the power-up mode, IDDQ may fail due to
high leakage current unless CEN is also driven HIGH.
Table 8
Driver Rise/Fall Slew Rate
Min. Typ. Max.
Unit
600
mV/ns
Output
40 pF
Input
GND
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