
15
Video ICs
BA7207AS / BA7207AK
Operation notes
(1) Equalizer fo adjustment
Set to PB mode and input a 25mV
P-P
, 1.0715MHz sine
wave to PBIN. Adjust the variable resistor connected
between FADJ1 and GND to maximize the REC OUT
output. This adjustment also adjusts the 1.1MHz and
2.2MHz band-pass filters. The value of the variable
resistor must be at least 2k
. If it is less than this,
adjustment may not be possible.
(2) Bell filter fo adjustment
Set to REC mode and input a 170mV
P-P
, 4.286MHz
sine wave to RECIN. Adjust the variable resistor con-
nected between FADJ2 and GND to maximize the
AMP OUT output. This adjustment also adjusts the
4.3MHz and 4.3MHz A and B band-pass filters. The
value of the variable resistor must be at least 2k
. If it
is less than this, adjustment may not be possible.
(3) Test pins
The MUL, DIV, LAO and 4XO pins are test terminals.
By connecting these pins to GND via a 3.6k
resistor,
it is possible to monitor there waveforms. When
unused, connect these pins to V
CC
to prevent interfer-
ence.
(4) REC / PB input levels
The frequency characteristics of the built-in filters can
change. For this reason use the following input signal
levels:
RECIN: 540mV
P-P
+ / – 6dB (cyan level)
PBIN: 75mV
P-P
+ / – 6dB (cyan level)
(5) Capacitor connected to VREG
Use a ceramic with a static capacitance of 0.1
μ
F. The
filter may not operate correctly with other capacitance
values.
(6) PBIN input
If there is a chroma component imposed on the FM
brightness signal, use a low-pass filter (with an fc of
about 2.2MHz) to remove the FM brightness signal
component, and ensure that only the chroma compo-
nent is input to PBIN.
(7) RECIN input
In the case of composite video input, connect a 100pF
capacitor to ensure that only the chroma component is
input to RECIN.
(8) Sync-gate phase adjustment
Perform fine adjustment of the sync-gate phase by
applying a voltage to the SGADJ terminal, or using a
resistor divider connected between V
CC
and GND. The
adjustment sensitivity is shown in Fig. 6.
SGADJ pin voltage when open: V
SGADJ
= 2.5V
Input impedance Z = 125k
1.5
2.5
3.5
+ 3.2
0
– 3.2
0.32
μ
S / 0.1V
SGADJ PIN APPLY VOLTAGE: V
SGADJ
(V)
G
D
μ
S
Fig. 8
Sync-gate phase