參數(shù)資料
型號(hào)： B250B57A106E1G
廠商： ON Semiconductor
文件頁數(shù)： 11/30頁
文件大小： 0K
描述： IC DSP AUDIO 16BIT 57CABGA
標(biāo)準(zhǔn)包裝： 2,500
系列： BelaSigna® 250
類型： 音頻處理器
應(yīng)用： 便攜式設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 57-VFBGA
供應(yīng)商設(shè)備封裝： 57-CABGA（5x5）
包裝： 帶卷 (TR)
BELASIGNA 250
http://onsemi.com
19
Memory Maps
Complete memory maps for BELASIGNA 250 are shown in Figure 6.
Figure 6. Memory Maps
P:0xFFFF
P:0x3FFF
P:0x3FF0
Interrupt Vectors
(16 x 16)
Program RAM
(12288 x 16)
P:0x1000
P Memory
P:0x03FF
P:0x0000
Program ROM
(1024 x 16)
Y Memory
X Memory
Y Data RAM
(4096 x 16)
Output FIFO
(384 x 16)
Smart Output FIFO
(384 x 16)
Digital Control Registers
(17 x 16)
Configuration Registers
(19 x 16)
Data Buffer
(17 x 16)
Control Register and
Y:0x4000
Y:0x4010
Y:0x403F
Y:0x404F
Y:0x8000
Y:0x8012
Y:0xFFFF
Y:0x1B7F
Y:0x1A00
Y:0x197F
Y:0x1800
Y:0x0FFF
Y:0x0000
Shifted by N_FFT
Access bits (17:2)
Access bits (16:1)
Access bits (15:0)
X:0x0000
X:0x0FFF
X Data RAM
(4096 x 16)
X:0x1000
X:0x10FF
Mirrored Temp. Memory
(256 x 18)
Mirrored Temp. Memory
(256 x 18)
Mirrored Temp. Memory
(256 x 18)
Mirrored Temp. Memory
(256 x 18)
Input FIFO
(384 x 16)
Smart Input FIFO
(384 x 16)
X:0xFFFF
Window
(192 x 16)
Gain
(256 x 16)
Microcode
(128 x 16)
ROM LUT
(128 x 16)
X:0x423F
X:0x4180
X:0x417F
X:0x4080
X:0x4000
X:0x407F
X:0x207F
X:0x2000
X:0x1B7F
X:0x1A00
X:0x197F
X:0x1800
X:0x13FF
X:0x1300
X:0x12FF
X:0x1200
X:0x11FF
X:0x1100
GeneralPurpose Timer
The generalpurpose timer is a 12bit countdown timer
with a 3bit prescaler that interrupts the RCore when it
reaches zero. It can operate in two modes, singleshot or
continuous. In singleshot mode, the timer counts down
only once and then generates an interrupt. It will then have
to be restarted from the RCore. In continuous mode, the
timer “wraps around” every time it hits zero and interrupts
are generated continuously. This unit is often useful in
scheduling tasks that are not part of the samplebased
signalprocessing scheme, such as checking a battery
voltage or reading the value of a volume control.
Watchdog Timer
The watchdog timer is a programmable hardware timer
that operates from the system clock and is used to ensure
system sanity. It is always active and must be periodically
acknowledged as a check that an application is still running.
Once the watchdog times out, it generates an interrupt. If left
to time out a second consecutive time without
acknowledgement, BELASIGNA 250 will fully reset itself.
Interrupts
The RCore has a single interrupt channel that serves 13
interrupt sources in a prioritized manner. The interrupt
controller also handles interrupt acknowledge flags. Every
interrupt source has its own interrupt vector. Furthermore,
the priority scheme of the interrupt sources can be modified.
Refer to Table 9 for a description of all interrupts.
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