參數(shù)資料
型號(hào)： AX88872P
廠商： ASIX Electronics Corporation
英文描述： 10/100BASE Dual Speed “Swipeater” Controller
中文描述： 一個(gè)10/100Base雙速“Swipeater”控制器
文件頁(yè)數(shù)： 9/36頁(yè)
文件大?。?/td> 399K
代理商： AX88872P
ASIX ELECTRONICS CORPORATION
9
CONFIDENTIAL
AX88872P Swipeater Controller PRELIMINARY
2.1.7 Repeater Port 6
Signal Name
SPEED6
Type
I
Pin No.
41
Description
Speed Select :
Please references section 2.1.1 PORT0 description.
CRS_DV6
I
42
Carrier Sense/Receive Data Valid :
Please references section 2.1.1
PORT0 description.
Receive Data :
Please references section 2.1.1 PORT0 description.
RXD6[1:0]
I
44,43
TXEN6
O
45
Transmit Enable :
Please references section 2.1.1 PORT0 description.
TXD6[1:0]
O
47,46
Transmit Data :
Please references section 2.1.1 PORT0 description.
2.1.8 Repeater Port 7
Signal Name
SPEED7
Type
I
Pin No.
49
Description
Speed Select :
Please references section 2.1.1 PORT0 description.
CRS_DV7
I
50
Carrier Sense/Receive Data Valid :
Please references section 2.1.1
PORT0 description.
Receive Data :
Please references section 2.1.1 PORT0 description.
RXD7[1:0]
I
52,51
TXEN7
O
53
Transmit Enable :
Please references section 2.1.1 PORT0 description.
TXD7[1:0]
O
55,54
Transmit Data :
Please references section 2.1.1 PORT0 description.
2.2 MII/RMII interface for switch ports
2.2.1 Switch Port 0
Signal Name
Type
STXEN0
O
Pin No.
87
Description
Transmit Enable :
STXEN0 is transition synchronously with respect
to the rising edge of STXCLK0. STXEN0 indicates that the port is
presenting nibbles on STXD0[3:0] for transmission.
When RMII mode, TXEN is transition synchronously with respect to
the rising edge of REF_CLK. STXEN0 indicates that the port is
presenting nibbles on STXD0[1:0] for transmission.
Transmit Data :
STXD0[3:0] is transition synchronously with respect
to the rising edge of STXCLK0. For each STXCLK period in which
STXEN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
When RMII mode, STXD0[1:0] shall transition synchronously to
REF_CLK. TXD0[1:0] shall be “00” to indicate idle when TX_EN is
disserted. Value other than “00” are reserved for out-of-band signaling
shall be ignored by PHY. When TX_EN is asserted, TXD[1:0] are
accepted for transmission by PHY
Transmit Clock :
STXCLK0 is a continuous clock that provides the
timing reference for the transfer of the STXEN0 and STXD0[3:0]
signals from the MII port the switch to the PHY.
Duplex Select :
DUPLEX0 is not standard MII/RMII signal. This
signal is source from PHY to inform switch whether 10M or 100M
speed is auto-negotiated.
Collision :
SCOL_SP0 is input from PHY, when collision is detected.
STXD0[3:0]
O
91,90,89,88
STXCLK0
I
93
SDUPLEX0
I
94
SCOL_SP0
I
97
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