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ASIX ELECTRONICS CORPORATION
3
AX88195 Local CPU Bus Fast Ethernet MAC Controller
6.4.5 68K Type I/O Access Timing.................................................................................................................... 27
6.4.6 8051 Bus Access Timing........................................................................................................................... 28
6.4.7 MII Timing............................................................................................................................................... 29
6.4.8 Asynchronous Memory I/F Access Timing................................................................................................ 30
7.0 PACKAGE INFORMATION........................................................................................................................... 31
APPENDIX A: APPLICATION NOTE 1............................................................................................................. 32
A.1 U
SING
C
RYSTAL
.............................................................................................................................................. 32
A.2 U
SING
O
SCILLATOR
......................................................................................................................................... 32
A.3 D
UAL POWER
(5V
AND
3.3V/3.0V)
APPLICATION
............................................................................................. 33
A.4 S
INGLE POWER
(3.3V/3.0V)
APPLICATION
........................................................................................................ 33
A.5 D
UAL POWER
(5V
AND
3.3V)
APPLICATION WITH
3.3V PHY............................................................................. 34
APPENDIX B: APPLICATION NOTE 2............................................................................................................. 35
B.1 A
DVANCE
A
PPLICATION FOR
U
SING
C
RYSTAL
................................................................................................... 35
APPENDIX C: APPLICATION NOTE FOR RDY IS NOT APPLICABLE ...................................................... 36
ERRATA OF AX88195 V1..................................................................................................................................... 37
FIGURES
F
IG
- 1 AX88195 B
LOCK
D
IAGRAM
............................................................................................................................. 4
F
IG
- 2 AX88195 P
IN
C
ONNECTION
D
IAGRAM
.............................................................................................................. 5
F
IG
- 3 AX88195 P
IN
C
ONNECTION
D
IAGRAM FOR
ISA B
US
M
ODE
............................................................................... 6
F
IG
- 4 AX88195 P
IN
C
ONNECTION
D
IAGRAM FOR
80
X
86 M
ODE
.................................................................................. 7
F
IG
- 5 AX88195 P
IN
C
ONNECTION
D
IAGRAM FOR
MC68K M
ODE
................................................................................ 8
F
IG
- 6 AX88195 P
IN
C
ONNECTION
D
IAGRAM FOR
MCS-51 M
ODE
............................................................................... 9
TABLES
T
AB
- 1 L
OCAL
CPU
BUS INTERFACE SIGNALS GROUP
.................................................................................................. 11
T
AB
- 2 MII
INTERFACE SIGNALS GROUP
..................................................................................................................... 11
T
AB
- 3 EEPROM
BUS INTERFACE SIGNALS GROUP
..................................................................................................... 12
T
AB
- 4 SRAM I
NTERFACE PINS GROUP
...................................................................................................................... 12
T
AB
- 5 M
ISCELLANEOUS PINS GROUP
......................................................................................................................... 13
T
AB
- 6 P
OWER ON
C
ONFIGURATION
S
ETUP
T
ABLE
..................................................................................................... 13
T
AB
- 7 I/O A
DDRESS
M
APPING
................................................................................................................................. 14
T
AB
- 8 L
OCAL
M
EMORY
M
APPING
............................................................................................................................ 14
T
AB
- 9 P
AGE
0
OF
MAC C
ORE
R
EGISTERS
M
APPING
.................................................................................................. 15
T
AB
- 10 P
AGE
1
OF
MAC C
ORE
R
EGISTERS
M
APPING
................................................................................................ 16