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ASIX ELECTRONICS CORPORATION
8
CONFIDENTIAL
AX88170 PRELIMINARY
SIGNAL
TYPE
PIN NO.
DESCRIPTION
nibbles on TXD [3:0] for transmission.
Transmit Data: TXD[3:0] is transition synchronously with respect to the
rising edge of TX_CLK. For each TX_CLK period in which TX_EN is
asserted ,TXD[3:0] are accepted for transmission by the PHY.
Transmit Clock: TX_CLK is a continuous clock from PHY. It provides the
timing reference for the transfer of the TX_EN and TXD[3:0] signals from
the MII port to the PHY.
Station Management Data Clock: The timing reference for MDIO. All data
transfers on MDIO are synchronized to the rising edge of this clock. MDC
is a 2.5MHz frequency clock output.
Station Management Data Input/Output: Serial data input/output transfers
from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII
specification.
TXD[3:0]
O
21, 20
19, 18
TX_CLK
I
16
MDC
O
12
MDIO
I/O/PU
14
Tab – 3 MII interface signals group (MAC mode)
2.3b MII interface signals group (PHY mode)
When /S_RMII=1 and /S_MAC=1
SIGNAL
TYPE
PIN NO.
RXD[3:0]
27, 26
CRS
O
15
DESCRIPTION
O
29, 28
Receive Data: Basically RXD[3:0] is transformed from TXD[3:0] of MAC
mode of MII interface.
Carrier Sense: Basically CRS is transformed from TX_EN of MAC mode of
MII interface.
Receive Data Valid: Basically RX_DV is transformed from TX_EN of MAC
mode of MII interface.
Receive Error: No used
Receive Clock: Basically RX_CLK is sourced from internal 25MHz local
clock.
Collision: this signal is generated by internal logic when collision is
detected.
Transmit Enable: Basically TX_EN is simulation from RX_DV of MAC
mode of MII interface.
Transmit Data: Basically TXD[3:0] is simulation from RXD[3:0] of MAC
mode of MII interface.
Transmit Clock: Basically TX_CLK is sourced from internal 25MHz local
clock.
RX_DV
O
32
RX_ER
RX_CLK
O
O
31
24
COL
O
13
TX_EN
I/PD
22
TXD[3:0]
I/PU
21, 20
19, 18
16
TX_CLK
O
Tab – 4 MII interface signals group (PHY mode)