PHCLK = (P1 + P2 * s + " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AX1000-FG676
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 90/262闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA AXCELERATOR 1M 676-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 40
绯诲垪锛� Axcelerator
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 12096
RAM 浣嶇附瑷�(j矛)锛� 165888
杓稿叆/杓稿嚭鏁�(sh霉)锛� 418
闁€鏁�(sh霉)锛� 1000000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 676-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 676-FBGA锛�27x27锛�
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Detailed Specifications
2- 4
R ev isio n 1 8
Ptotal = Pdc + Pac
PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs
PCLK = (P4 + P5 * s + P6 * sqrt[s]) * Fs
PR-cells = P7 * ms * Fs
PC-cells = P8 * mc * Fs
Pinputs = P9 * pi * Fpi
Table 2-5 Different Components Contributing to the Total Power Consumption in Axcelerator Devices
Component
Definition
Device Specific Value (in W/MHz)
AX125 AX250 AX500 AX1000 AX2000
P1
Core tile HCLK power component
33
49
71
130
216
P2
R-cell power component
0.2
P3
HCLK signal power dissipation
4.5
9
13.5
18
P4
Core tile RCLK power component
33
49
71
130
216
P5
R-cell power component
0.3
P6
RCLK signal power dissipation
6.5
13
19.5
26
P7
Power dissipation due to the switching activity on the R-cell
1.6
P8
Power dissipation due to the switching activity on the C-cell
1.4
P9
Power component associated with the input voltage
10
P10
Power component associated with the output voltage
See table Per pin contribution
P11
Power component associated with the read operation in the
RAM block
25
P12
Power component associated with the write operation in
the RAM block
30
P13
Core PLL power component
1.5
Pdc = ICCA * VCCA
Pac =PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory + PPLL
s
= the number of R-cells clocked by this clock
Fs
= the clock frequency
s
= the number of R-cells clocked by this clock
Fs
= the clock frequency
ms = the number of R-cells switching at each Fs cycle
Fs
= the clock frequency
mc = the number of C-cells switching at each Fs cycle
Fs
= the clock frequency
pi
= the number of inputs
Fpi = the average input frequency
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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AX1000-FG676I 鍔熻兘鎻忚堪:IC FPGA AXCELERATOR 1M 676-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:Axcelerator 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�(j矛):6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛�
AX1000-FG676M 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA Axcelerator Family 612K Gates 12096 Cells 649MHz 0.15um Technology 1.5V 676-Pin FBGA 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:FPGA AXCELERATOR 612K GATES 12096 CELLS 649MHZ 0.15UM 1.5V 6 - Trays
AX1000-FG896 鍔熻兘鎻忚堪:IC FPGA AXCELERATOR 1M 896-FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄e垪锛� 绯诲垪:Axcelerator 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�(j矛):6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛�
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