80h(2) INDF Addressing this location " />
參數(shù)資料
型號: ATTINY4313-PU
廠商: Atmel
文件頁數(shù): 4/22頁
文件大?。?/td> 0K
描述: IC MCU AVR 4K FLASH 20PDIP
產(chǎn)品培訓模塊: MCU Product Line Introduction
tinyAVR Introduction
標準包裝: 18
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 18
程序存儲器容量: 4KB(2K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
配用: ATSTK600-SC01-ND - STK600 DIP SOCKET CARD AVR
PIC16F872
DS30221C-page 10
2006 Microchip Technology Inc.
Bank 1
80h(2)
INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
0000 0000
81h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(2)
PCL
Program Counter (PC) Least Significant Byte
0000 0000
83h(2)
STATUS
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
84h(2)
FSR
Indirect data memory address pointer
xxxx xxxx
85h
TRISA
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111
88h
Unimplemented
89h
Unimplemented
8Ah(1,2)
PCLATH
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh(2)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
8Ch
PIE1
(3)
ADIE
(3)
SSPIE
CCP1IE
TMR2IE
TMR1IE
r0rr 0000
8Dh
PIE2
(3)
—EEIE
BCLIE
(3)
-r-0 0--r
8Eh
PCON
—POR
BOR
---- --qq
8Fh
Unimplemented
90h
Unimplemented
91h
SSPCON2
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
0000 0000
92h
PR2
Timer2 Period Register
1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
94h
SSPSTAT
SMP
CKE
D/A
PS
R/W
UA
BF
0000 0000
95h
Unimplemented
96h
Unimplemented
97h
Unimplemented
95h
Unimplemented
95h
Unimplemented
9Ah
Unimplemented
9Bh
Unimplemented
9Ch
Unimplemented
9Dh
Unimplemented
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx
9Fh
ADCON1
ADFM
PCFG3
PCFG2
PCFG1
PCFG0
0--- 0000
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Details
on
page:
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are
transferred to the upper byte of the program counter.
2:
These registers can be addressed from any bank.
3:
These bits are reserved; always maintain these bits clear.
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