參數(shù)資料
型號: ATTINY15L-1SU
廠商: Atmel
文件頁數(shù): 13/85頁
文件大?。?/td> 0K
描述: IC MCU AVR 1K FLASH 1.6MHZ 8SOIC
標(biāo)準(zhǔn)包裝: 95
系列: AVR® ATtiny
核心處理器: AVR
芯體尺寸: 8-位
速度: 1.6MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲器容量: 1KB(512 x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 64 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.209",5.30mm 寬)
包裝: 管件
20
ATtiny15L
1187H–AVR–09/07
The corresponding interrupt of External Interrupt Request 0 is executed from Program
memory address $001. See also “External Interrupts.”
Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the interrupt on pin change is enabled. Any change on any input or I/O pin will cause an
interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from
Program memory address $002. See also “Pin Change Interrupt.”
Bits 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and always read as zero.
The General Interrupt Flag
Register – GIFR
Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
Bit 6 – INTF0: External Interrupt Flag0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the
MCU will jump to the Interrupt Vector at address $001. The flag is cleared when the
interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical “1”
to it. The flag is always cleared when INT0 is configured as level interrupt.
Bit 5 – PCIF: Pin Change Interrupt Flag
When an event on any input or I/O pin triggers an interrupt request, PCIF becomes set
(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to
the Interrupt Vector at address $002. The flag is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing a logical “1” to it.
Bits 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and always read as zero.
The Timer/Counter Interrupt
Mask Register – TIMSK
Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny15L and always reads as zero.
Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare Match, interrupt is enabled. The corresponding interrupt (at
Bit
7
65
43
2
1
0
$3A
INTF0
PCIF
–––
GIFR
Read/Write
R
R/W
R
Initial Value
0
Bit
7
6
5
4
3
2
1
0
$39
OCIE1A
TOIE1
TOIE0
TIMSK
Read/Write
R
R/W
R
R/W
R
Initial Value
0
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