參數(shù)資料
型號(hào): ATSAM3X8CA-AU
廠商: Atmel
文件頁(yè)數(shù): 21/71頁(yè)
文件大小: 0K
描述: IC MCU 2X256KB CORTEX-M3 100-QFP
標(biāo)準(zhǔn)包裝: 90
系列: SAM3X
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 84MHz
連通性: CAN,以太網(wǎng),I²C,IrDA,LIN,MMC,SPI,SSC,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 63
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 96K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 1.95 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
30
11057BS–ATARM–13-Jul-12
SAM3X/A
30
11057BS–ATARM–13-Jul-12
SAM3X/A
Note:
1. If PC0 is used as PIO input in user applications, a low level must be ensured at startup to pre-
vent Flash erase before the user application sets PC0 into PIO mode.
6.2.1
Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on
a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference
and reset state, refer to Table 3-1.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging
probe. Please refer to the “Debug and Test” section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users with more general input/output pins
when the debug port is not needed in the end application. Mode selection between SWJ-DP
mode (System IO mode) and general IO mode is performed through the AHB Matrix Special
Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing
and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 k
Ω to GND, so that it can be left uncon-
nected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire
Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous
trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and
JTAG-DP switching, please refer to the “Debug and Test” section of the product datasheet.
All JTAG signals are supplied with VDDIO except JTAGSEL, supplied by VDDBU.
6.3
Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming
mode of the SAM3X/A series. The TST pin integrates a permanent pull-down resistor of about
15 k
Ω to GND, so that it can be left unconnected for normal operations. To enter fast program-
ming mode, see the “Fast Flash Programming Interface” section. For more information on the
manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet.
Table 6-1.
System I/O Configuration Pin List
SYSTEM_IO
Bit Number
Peripheral
Default Function
After Reset
Other Function
Constraints for
Normal Start
Configuration
12
-
ERASE
PC0
Low Level at
startup
In Matrix User Interface Registers
(Refer to “System IO Configuration
Register“ in the “Bus Matrix“ section
of the product datasheet.)
A
TCK/SWCLK
PB28
-
In PIO Controller
A
TDI
PB29
-
A
TDO/TRACESWO
PB30
-
A
TMS/SWDIO
PB31
-
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