參數(shù)資料
型號(hào)： ATSAM3N4BA-MU
廠商： Atmel
文件頁(yè)數(shù)： 18/60頁(yè)
文件大?。?/td> 0K
描述： MCU FLASH 64-QFN
產(chǎn)品培訓(xùn)模塊： Touch Solutions on the Atmel ARM? Cortex?-M3 Based Flash Microcontrollers
特色產(chǎn)品： SAM3N Flash MCU
標(biāo)準(zhǔn)包裝： 260
系列： SAM3N
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 48MHz
連通性： I²C，IrDA，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 47
程序存儲(chǔ)器容量： 256KB（256K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
RAM 容量： 24K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x10b，D/A 1x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-VFQFN 裸露焊盤(pán)
包裝： 托盤(pán)
25
11011BS–ATARM–22-Feb-12
SAM3N Summary
Notes:
1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the
user application sets PB12 into PIO mode.
2. In the product Datasheet Refer to: Slow Clock Generator of the Supply Controller section.
3. In the product Datasheet Refer to: 3 to 20 MHZ Crystal Oscillator information in the PMC section.
6.2.1
Serial Wire JTAG Debug Port (SWJ-DP) Pins
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on
a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference
and reset state, refer to Table 3-1 on page 7.
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging
probe. Please refer to the Debug and Test Section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins
when the debug port is not needed in the end application. Mode selection between SWJ-DP
mode (System IO mode) and general IO mode is performed through the AHB Matrix Special
Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing
and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 k
Ω to GND, so that it can be left uncon-
nected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire
Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous
trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and
JTAG-DP switching, please refer to the Debug and Test Section.
Table 6-1.
System I/O Configuration Pin List.
SYSTEM_IO
bit number
Default function
after reset
Other function
Constraints for
normal start
Configuration
12
ERASE
PB12
Low Level at
startup(1)
In Matrix User Interface Registers
(Refer to the System I/O
Configuration Register in the Bus
Matrix section of the product
datasheet.)
7
TCK/SWCLK
PB7
-
6
TMS/SWDIO
PB6
-
5
TDO/TRACESWO
PB5
-
4
TDI
PB4
-
PA7
XIN32
-
See footnote (2) below
-
PA8
XOUT32
-
PB9
XIN
-
See footnote (3) below
-
PB8
XOUT
-
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