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| 型號： | ATS617LSGTN-T |
| 廠商： | Allegro Microsystems Inc |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 489K |
| 描述： | IC HALL EFFECT GEAR SENSOR 4SIP |
| 產(chǎn)品培訓(xùn)模塊： | Current Sensor |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 傳感范圍： | 60G |
| 類型： | 專用型 |
| 電源電壓： | 4.5 V ~ 24 V |
| 電流 - 電源： | 12mA |
| 電流 - 輸出（最大）： | 55mA |
| 輸出類型： | 數(shù)字，開路集電極 |
| 特點(diǎn)： | 輪齒類型 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 4-SIP |
| 供應(yīng)商設(shè)備封裝： | 4-SIP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1142 (CN2011-ZH PDF) |
| 其它名稱： | 620-1326-6 |
Dynamic, Self-Calibrating, Peak-Detecting, Differential
Hall Effect Gear Tooth Sensor IC
ATS617LSG
14
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Power Derating
The device must be operated below the maximum junction
temperature of the device, T
J(max)
. Under certain combinations of
peak conditions, reliable operation may require derating supplied
power or improving the heat dissipation properties of the appli-
cation. This section presents a procedure for correlating factors
affecting operating T
J
. (Thermal data is also available on the
Allegro MicroSystems website.)
The Package Thermal Resistance, R
qJA
, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity, K,
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, R
qJC
, is relatively
small component of R
qJA
. Ambient air temperature, T
A
, and air
motion are significant external factors, damped by overmolding.
The effect of varying power levels (Power Dissipation, P
D
), can
be estimated. The following formulas represent the fundamental
relationships used to estimate T
J
, at P
D
.
P
D
= V
IN
?/DIV>
I
IN
(1)
DT = P
D
?/DIV>
R
qJA
(2)
T
J
= T
A
+ 擳
(3)
For example, given common conditions such as: T
A
= 25癈,
V
CC
= 12 V, I
CC
= 6 mA, and R
qJA
= 126 癈/W, then:
P
D
= V
CC
?/DIV>
I
CC
= 12 V
?/DIV>
6 mA = 72 mW
DT = P
D
?/DIV>
R
qJA
= 72 mW
?/DIV>
126 癈/W = 9癈
T
J
= T
A
+ DT = 25癈 + 9癈 = 34癈
A worst-case estimate, P
D
(max), represents the maximum allow-
able power level (V
CC
(max), I
CC
(max)), without exceeding
T
J
(max), at a selected R
qJA
and T
A
.
Example: Reliability for V
CC
at T
A
=
150癈, package SG, using
minimum-K PCB.
Observe the worst-case ratings for the device, specifically:
R
qJA
=
126 癈/W, T
J
(max)
=
165癈, V
CC
(max)
=
24
V, and
I
CC
(max)
=
12
mA.
Calculate the maximum allowable power level, P
D
(max). First,
invert equation 3:
DT
max
= T
J
(max) T
A
= 165
癈
150
癈 = 15
癈
This provides the allowable increase to T
J
resulting from internal
power dissipation. Then, invert equation 2:
P
D
(max)
= DT
max
?R
qJA
= 15癈 ?126 癈/W = 119 mW
Finally, invert equation 1 with respect to voltage:
V
CC
(est) = P
D
(max)
? I
CC
(max) = 119 mW ?12 mA = 9.92 V
The result indicates that, at T
A
, the application and device can
dissipate adequate amounts of heat at voltages d V
CC
(est).
Compare V
CC
(est) to V
CC
(max). If V
CC
(est) d V
CC
(max), then
reliable operation between V
CC
(est) and V
CC
(max) requires
enhanced R
qJA
. If V
CC
(est) e V
CC
(max), then operation between
V
CC
(est) and V
CC
(max) is reliable under these conditions.
This value applies only to the voltage drop across the ATS617
chip. If a protective series diode or resistor is used, the effec-
tive maximum supply voltage is increased. For example, when a
standard diode with a 0.7 V drop is used:
V
CC
(max) = 9.9 V + 0.7 V = 10.6 V
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