I2C MAST" />
    參數(shù)資料
    型號(hào): ATMEGA649V-8AI
    廠商: Atmel
    文件頁(yè)數(shù): 24/146頁(yè)
    文件大?。?/td> 0K
    描述: IC AVR MCU FLASH 64K 1.8V 64TQFP
    產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
    標(biāo)準(zhǔn)包裝: 90
    系列: AVR® ATmega
    核心處理器: AVR
    芯體尺寸: 8-位
    速度: 8MHz
    連通性: SPI,UART/USART,USI
    外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LCD,POR,PWM,WDT
    輸入/輸出數(shù): 53
    程序存儲(chǔ)器容量: 64KB(32K x 16)
    程序存儲(chǔ)器類(lèi)型: 閃存
    EEPROM 大?。?/td> 2K x 8
    RAM 容量: 4K x 8
    電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 64-TQFP
    包裝: 托盤(pán)
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    PIC16(L)F1825/1829
    DS41440C-page 272
    2010-2012 Microchip Technology Inc.
    25.6
    I2C MASTER MODE
    Master mode is enabled by setting and clearing the
    appropriate SSPM bits in the SSPxCON1 register and
    by setting the SSPEN bit. In Master mode, the SDAx
    and SCKx pins must be configured as inputs. The
    MSSP peripheral hardware will override the output
    driver TRIS controls when necessary to drive the pins
    low.
    Master mode of operation is supported by interrupt
    generation on the detection of the Start and Stop
    conditions. The Stop (P) and Start (S) bits are cleared
    from a Reset or when the MSSPx module is disabled.
    Control of the I2C bus may be taken when the P bit is
    set, or the bus is Idle.
    In Firmware Controlled Master mode, user code
    conducts all I2C bus operations based on Start and
    Stop bit condition detection. Start and Stop condition
    detection is the only active circuitry in this mode. All
    other communication is done by the user software
    directly manipulating the SDAx and SCLx lines.
    The following events will cause the SSPx Interrupt Flag
    bit, SSPxIF, to be set (SSPx interrupt, if enabled):
    Start condition detected
    Stop condition detected
    Data transfer byte transmitted/received
    Acknowledge transmitted/received
    Repeated Start generated
    25.6.1
    I2C MASTER MODE OPERATION
    The master device generates all of the serial clock
    pulses and the Start and Stop conditions. A transfer is
    ended with a Stop condition or with a Repeated Start
    condition. Since the Repeated Start condition is also
    the beginning of the next serial transfer, the I2C bus will
    not be released.
    In Master Transmitter mode, serial data is output
    through SDAx, while SCLx outputs the serial clock. The
    first byte transmitted contains the slave address of the
    receiving device (7 bits) and the Read/Write (R/W) bit.
    In this case, the R/W bit will be logic ‘0’. Serial data is
    transmitted eight bits at a time. After each byte is
    transmitted, an Acknowledge bit is received. Start and
    Stop conditions are output to indicate the beginning
    and the end of a serial transfer.
    In Master Receive mode, the first byte transmitted
    contains the slave address of the transmitting device
    (7 bits) and the R/W bit. In this case, the R/W bit will be
    logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
    address followed by a ‘1’ to indicate the receive bit.
    Serial data is received via SDAx, while SCLx outputs
    the serial clock. Serial data is received eight bits at a
    time. After each byte is received, an Acknowledge bit is
    transmitted. Start and Stop conditions indicate the
    beginning and end of transmission.
    A Baud Rate Generator is used to set the clock
    frequency output on SCLx. See Section 25.7 “Baud
    for more detail.
    Note 1:
    The MSSPx module, when configured in
    I2C Master mode, does not allow
    queueing of events. For instance, the user
    is not allowed to initiate a Start condition
    and immediately write the SSPxBUF
    register to initiate transmission before the
    Start condition is complete. In this case,
    the SSPxBUF will not be written to and the
    WCOL bit will be set, indicating that a
    write to the SSPxBUF did not occur
    2:
    When
    in
    Master
    mode,
    Start/Stop
    detection is masked and an interrupt is
    generated when the SEN/PEN bit is
    cleared and the generation is complete.
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