參數(shù)資料
型號(hào): ATMEGA328P-15AZ
廠商: Atmel
文件頁(yè)數(shù): 48/83頁(yè)
文件大?。?/td> 0K
描述: MCU AVR 32K FLASH 15MHZ 32-TQFP
產(chǎn)品培訓(xùn)模塊: megaAVR Introduction
標(biāo)準(zhǔn)包裝: 1
系列: AVR® ATmega
核心處理器: AVR
芯體尺寸: 8-位
速度: 16MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 32-TQFP
包裝: 剪切帶 (CT)
其它名稱(chēng): ATMEGA328P-15AZCT
PIC12(L)F1822/PIC16(L)F1823
DS41413C-page 210
2010-2012 Microchip Technology Inc.
24.3
PWM Overview
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
Figure 24-3 shows a typical waveform of the PWM
signal.
24.3.1
STANDARD PWM OPERATION
The standard PWM mode generates a Pulse-Width
modulation (PWM) signal on the CCP1 pin with up to 10
bits of resolution. The period, duty cycle, and resolution
are controlled by the following registers:
PR2 registers
T2CON registers
CCPR1L registers
CCP1CON registers
Figure 24-4 shows a simplified block diagram of PWM
operation.
FIGURE 24-3:
CCP1 PWM OUTPUT
SIGNAL
FIGURE 24-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
Note 1:
The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCP1 pin.
2:
Clearing the CCP1CON register will
relinquish control of the CCP1 pin.
Period
Pulse Width
TMR2 = 0
TMR2 = CCPR1H:CCP1CON<5:4>
TMR2 = PR2
CCPR1L
CCPR1H(2) (Slave)
Comparator
TMR2
PR2
(1)
RQ
S
Duty Cycle Registers
CCP1CON<5:4>
Clear Timer,
toggle CCP1 pin and
latch duty cycle
Note
1:
The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
two bits of the prescaler, to create the 10-bit
time base.
2:
In PWM mode, CCPR1H is a read-only register.
TRIS
CCP1
Comparator
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