The Functional Logic Diagram de" />
參數(shù)資料
型號(hào): ATF22LV10CZ-25XC
廠商: Atmel
文件頁(yè)數(shù): 18/19頁(yè)
文件大小: 0K
描述: IC PLD 25NS 24TSSOP
標(biāo)準(zhǔn)包裝: 62
系列: 22V10
可編程類型: EE PLD
宏單元數(shù): 10
輸入電壓: 3.3V
速度: 25ns
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
其它名稱: ATF22LV10CZ25XC
8
0779M–PLD–7/10
Atmel ATF22LV10C(Q)Z
Figure 8-2.
I/O Diagram
9.
Functional Logic Diagram Description
The Functional Logic Diagram describes the Atmel ATF22LV10CZ/CQZ architecture.
The ATF22LV10CZ/CQZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured into one of four
output configurations: active high/low or registered/combinatorial. The universal architecture of the
ATF22LV10CZ/CQZ can be programmed to emulate most 24-pin PAL devices.
Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse,
when programmed, protects the contents of the ATF22LV10CZ/CQZ. Eight bytes (64-fuses) of User Signature are
accessible to the user for purposes such as storing project name, part number, revision or date. The User
Signature is accessible regardless of the state of the security fuse.
100K
VCC
DATA
OE
I/O
INPUT
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