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參數(shù)資料
| 型號(hào)： | ATF20V8BQL-15XC |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 18/22頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD 15NS 24TSSOP |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 系列： | 20V8 |
| 可編程類(lèi)型： | EE PLD |
| 宏單元數(shù)： | 8 |
| 輸入電壓： | 5V |
| 速度： | 15ns |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 其它名稱(chēng)： | ATF20V8BQL15XC |
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ATF20V8B(Q)(L)
5
Input Test Waveforms and
Measurement Levels
t
R, tF < 5 ns (10% to 90%)
Output Test Loads
Commercial
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF20V8Bs are designed to reset dur-
ing power-up. At a point delayed slightly from V
CC crossing
V
RST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
CC actually rises in the system, the fol-
lowing conditions are required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3.
The clock must remain stable during t
PR.
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF20V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Programming/erasing is performed using standard PLD
programmers. For further information, see the Configurable
Logic Databook, section titled, “CMOS PLD Programming
Hardware and Software Support.”
Pin Capacitance
f = 1 MHz, T = 25°C
Typ
Max
Units
Conditions
CIN
58
pF
VIN = 0V
C
OUT
68
pF
V
OUT = 0V
Parameter
Description
Typ
Max
Units
tPR
Power-up Reset Time
600
1,000
ns
V
RST
Power-up Reset Voltage
3.8
4.5
V
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