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參數(shù)資料
| 型號： | ATF16V8C-7XU |
| 廠商： | Atmel |
| 文件頁數(shù)： | 23/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD 7NS 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 系列： | 16V8 |
| 可編程類型： | EE PLD |
| 宏單元數(shù)： | 8 |
| 輸入電壓： | 5V |
| 速度： | 7ns |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
9
0425H–PLD–3/11
Atmel ATF16V8C
In simple mode, all feedback paths of the output pins are routed via the adjacent pins. In doing so, the two inner most pins
(pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output.
16.1
Atmel ATF16V8C registered mode
PAL device emulation/PAL replacement. The registered mode is used if one or more registers are required. Each
macrocell can be configured as either a registered or combinatorial output or I/O, or as an input. For a registered output or
I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin. Eight product terms are allocated to
the sum term. For a combinatorial output or I/O, the output enable is controlled by a product term, and seven product
terms are allocated to the sum term. When the macrocell is configured as an input, the output enable is permanently
disabled.
Any register usage will make the compiler select this mode. The following registered devices can be emulated using this
mode:
16R8
16RP8
16R6
16RP6
16R4
16RP4
Figure 17.
Registered configuration for registered mode
Notes:
1. Pin 1 controls common CLK for the registered outputs.
Pin 11 controls common OE for the registered outputs.
Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin usage automatically.
Figure 18.
Combinatorial configuration for registered mode
Notes:
1. Pin 1 and Pin 11 are permanently configured as CLK and OE.
2. The development software configures all the architecture control bits and checks for proper pin usage automatically.
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