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參數(shù)資料
| 型號(hào)： | ATF16V8B-10SC |
| 廠商： | Atmel |
| 文件頁數(shù)： | 24/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD EE 10NS 20-SOIC |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 系列： | 16V8 |
| 可編程類型： | EE PLD |
| 宏單元數(shù)： | 8 |
| 輸入電壓： | 5V |
| 速度： | 10ns |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 管件 |
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7
0364J–PLD–7/05
ATF16V8B/BQ/BQL
4.6
Power-up Reset
The registers in the ATF16V8Bs are designed to reset during power-up. At a point delayed
slightly from V
CC crossing VRST, all registers will be reset to the low state. As a result, the regis-
tered output state will always be high on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how V
CC actually rises in the system, the following conditions are
required:
1.
The V
CC rise must be monotonic,
2.
After reset occurs, all input and feedback setup times must be met before driving the
clock pin high, and
3.
The clock must remain stable during t
PR.
Figure 4-1.
Power-up Reset Waveforms
4.7
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either
a high or a low. This feature will simplify testing since any state can be forced into the registers
to control test sequencing. A JEDEC file with preload is generated when a source file with vec-
tors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically
by most of the approved programmers after the programming.
5.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying of the ATF16V8B fuse patterns. Once
programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains
accessible.
The security fuse should be programmed last, as its effect is immediate.
Table 4-2.
Power-up Reset Parameters
Parameter
Description
Typ
Max
Units
t
PR
Power-up
Reset Time
600
1,000
ns
VRST
Power-up
Reset Voltage
3.8
4.5
V
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| ATF16V8B-10SI | 功能描述:EEPLD - 電子擦除可編程邏輯設(shè)備 10NS 250 GATES EPLD 10NS IND TEMP RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數(shù)量:20 電源電流:20 mA 延遲時(shí)間:15 ns 每個(gè)宏指令的積項(xiàng)數(shù):8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池?cái)?shù)量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-20 |
| ATF16V8B-10XC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Highperformance EE PLD |
| ATF16V8B-10XI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| ATF16V8B-15GC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
| ATF16V8B-15GI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable PLD |
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